JPS5745788A - Televison signal processing device - Google Patents
Televison signal processing deviceInfo
- Publication number
- JPS5745788A JPS5745788A JP12088280A JP12088280A JPS5745788A JP S5745788 A JPS5745788 A JP S5745788A JP 12088280 A JP12088280 A JP 12088280A JP 12088280 A JP12088280 A JP 12088280A JP S5745788 A JPS5745788 A JP S5745788A
- Authority
- JP
- Japan
- Prior art keywords
- difference
- value
- coefficient
- frames
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
- H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
Abstract
PURPOSE:To reduce generation of information between frames and improve the quality of picture by determining the value of coefficient by which the difference between frames is to be multiplied in coding between frames by value of multiplicication coefficient of one frame before, the difference between frames and a controlling signal from outside. CONSTITUTION:Digitized TV signals are inputted to a signal input terminal and the value of output picture element of a frame delay circuit 3 is subtracted by a subtracter 2 to find out the difference and inputted to a multiplier 4. the difference value from the subtracter 2, control signals from a control signal input terminal 9, and multiplication coefficient delayed by one frame by a frame delay circuit 8 are inputted to a coefficient setting circuit 5. A coefficient by which the difference is to be multiplied is determined by the circuit 5 add inputted to the multiplier 4. The difference value is multiplied by a coefficient smaller than 1, and not negative, determined by the circuit 5 to suppress the difference value and a picture element value of output of the circuit 3 is added by an adder 6. Thus, the amount of generated information is reduced and picture quality of coding between frames is improved.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12088280A JPS5745788A (en) | 1980-09-01 | 1980-09-01 | Televison signal processing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12088280A JPS5745788A (en) | 1980-09-01 | 1980-09-01 | Televison signal processing device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5745788A true JPS5745788A (en) | 1982-03-15 |
Family
ID=14797298
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12088280A Pending JPS5745788A (en) | 1980-09-01 | 1980-09-01 | Televison signal processing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5745788A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02132641U (en) * | 1989-04-07 | 1990-11-05 |
-
1980
- 1980-09-01 JP JP12088280A patent/JPS5745788A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02132641U (en) * | 1989-04-07 | 1990-11-05 |
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