JPS5744327A - Pulse increasing circuit for clock pulse signal - Google Patents
Pulse increasing circuit for clock pulse signalInfo
- Publication number
- JPS5744327A JPS5744327A JP11925080A JP11925080A JPS5744327A JP S5744327 A JPS5744327 A JP S5744327A JP 11925080 A JP11925080 A JP 11925080A JP 11925080 A JP11925080 A JP 11925080A JP S5744327 A JPS5744327 A JP S5744327A
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- clock pulse
- clock
- output
- rise
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/00006—Changing the frequency
Abstract
PURPOSE:To increase high-speed clock pulses with a pulse increase signal outputted from an equipment whose operation speed is low by synchronously shaping the pulse increase signal to one period width of the clock pulses and by exclusively ORing the shaped signal with the clock pulses. CONSTITUTION:At the rise of a pulse increase signal, a D type flip-flop (D-FF)111 is set and at the following fall of the clock pulse, a JK type flip-flop (JK-FF)12 reads the output of the D-FF111. At the rise of the next clock pulse, D-FF112 is set, so the output Q' goes to a level L, resetting the D-FF111. Then, the output of the JK-FF12 is inverted at the fall of the clock pulse and the D-FF112 is reset at the rise of the next clock pulse. The output Q' is applied to an exclusive OR circuit 17 through a delay circuit 16 to be exclusively ORed with the clock pulse thereby increasing one clock pulse.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11925080A JPS5744327A (en) | 1980-08-29 | 1980-08-29 | Pulse increasing circuit for clock pulse signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11925080A JPS5744327A (en) | 1980-08-29 | 1980-08-29 | Pulse increasing circuit for clock pulse signal |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5744327A true JPS5744327A (en) | 1982-03-12 |
Family
ID=14756671
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11925080A Pending JPS5744327A (en) | 1980-08-29 | 1980-08-29 | Pulse increasing circuit for clock pulse signal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5744327A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4814636A (en) * | 1987-12-09 | 1989-03-21 | Xerox Corporation | Full pixel pulse stretching for phase reversal scophony transmission |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51142947A (en) * | 1975-06-03 | 1976-12-08 | Furuno Electric Co Ltd | Synthesizer of two frequencies |
JPS51142948A (en) * | 1975-06-03 | 1976-12-08 | Furuno Electric Co Ltd | Synthesizer of two frequencies |
-
1980
- 1980-08-29 JP JP11925080A patent/JPS5744327A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51142947A (en) * | 1975-06-03 | 1976-12-08 | Furuno Electric Co Ltd | Synthesizer of two frequencies |
JPS51142948A (en) * | 1975-06-03 | 1976-12-08 | Furuno Electric Co Ltd | Synthesizer of two frequencies |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4814636A (en) * | 1987-12-09 | 1989-03-21 | Xerox Corporation | Full pixel pulse stretching for phase reversal scophony transmission |
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