JPS5744280A - Microprocessor - Google Patents
MicroprocessorInfo
- Publication number
- JPS5744280A JPS5744280A JP55118735A JP11873580A JPS5744280A JP S5744280 A JPS5744280 A JP S5744280A JP 55118735 A JP55118735 A JP 55118735A JP 11873580 A JP11873580 A JP 11873580A JP S5744280 A JPS5744280 A JP S5744280A
- Authority
- JP
- Japan
- Prior art keywords
- cash
- memory
- register
- gamma
- beta
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microcomputers (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE:To incorporate a cash memory, by constituting the cash memory so as to function as a cash as well as an associative memory. CONSTITUTION:The address data within a semiassociative cash 12 is selected by a lower bit gamma and its upper bit beta of a memory address which is set to a memory address register 13. Then the output of selection is supplied to an input Y of a comparator 41. On the other hand, an upper bit alpha of the memory address is supplied to an input terminal X of the comparator 41. If a coincidence of comparison is obtained here, an output Z at te DATA side of the cash 12 selected by the bits beta and gamma is delivered to an instruction register 14. In the same way, the data fetched from a main storage is stored in the DATA side of the entry designated by the beta and gamma of the register 13. At the same time, the bit alpha of the register 13 at that time is stored in an ADRS. In such way, the cash 12 has the functions of cash memory together with an associative memory.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55118735A JPS5744280A (en) | 1980-08-28 | 1980-08-28 | Microprocessor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55118735A JPS5744280A (en) | 1980-08-28 | 1980-08-28 | Microprocessor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5744280A true JPS5744280A (en) | 1982-03-12 |
Family
ID=14743769
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55118735A Pending JPS5744280A (en) | 1980-08-28 | 1980-08-28 | Microprocessor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5744280A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02187881A (en) * | 1989-01-13 | 1990-07-24 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
-
1980
- 1980-08-28 JP JP55118735A patent/JPS5744280A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02187881A (en) * | 1989-01-13 | 1990-07-24 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5744280A (en) | Microprocessor | |
JPS56166551A (en) | Operation control | |
JPS56111961A (en) | Data file control device | |
JPS5617489A (en) | Character display processing system | |
TW345637B (en) | Data processor with branch target address cache and method of operation a data processor has a BTAC storing a number of recently encountered fetch address-target address pairs. | |
JPS576925A (en) | Priority selecting circuit | |
GB1167336A (en) | Improvements in or relating to Data Processing Devices | |
JPS6433641A (en) | Input/output system for external memory | |
JPS5710853A (en) | Memory device | |
JPS6453240A (en) | Evaluating microprocessor | |
JPS5577069A (en) | Data memory system | |
JPS5785148A (en) | Instruction sequence control device | |
JPS5733472A (en) | Memory access control system | |
JPS5523555A (en) | Micro cash system having resident bit | |
JPS57179982A (en) | Memory device | |
JPS5775350A (en) | Input/output data convertor | |
JPS55115159A (en) | Information processing unit | |
JPS56134384A (en) | Memory access system | |
JPS5798051A (en) | Memory system of scan in/out data | |
JPS5599652A (en) | Microprogram control unit | |
JPS55121543A (en) | Area decision circuit | |
JPS5451748A (en) | Calculator | |
JPS55117780A (en) | Buffer memory unit | |
IT1027347B (en) | Electronic computer using micro-programme routine stored in ROM - includes random access memory which is used to hold address instructions from keyboard | |
IT1048204B (en) | Electronic computer using micro-programme routine stored in ROM - includes random access memory which is used to hold address instructions from keyboard |