JPS573457A - Level detecting circuit - Google Patents

Level detecting circuit

Info

Publication number
JPS573457A
JPS573457A JP7713380A JP7713380A JPS573457A JP S573457 A JPS573457 A JP S573457A JP 7713380 A JP7713380 A JP 7713380A JP 7713380 A JP7713380 A JP 7713380A JP S573457 A JPS573457 A JP S573457A
Authority
JP
Japan
Prior art keywords
signal
alarm information
terminal
input
transmit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7713380A
Other languages
Japanese (ja)
Inventor
Kazuo Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7713380A priority Critical patent/JPS573457A/en
Publication of JPS573457A publication Critical patent/JPS573457A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To transmit an alarm information signal with the same circuit constitution for an input from a low to high frequency, by comparing an input signal remaining as an AC signal with a reference potential to transmit the alarm information signal for digital processing. CONSTITUTION:An input signal (a) applied to an input terminal 1 is given to comparators 14-1 and 14-2 via a capacitor 2. The comparator 14-1 outputs an inversion signal as an output signal (d), and the comparator 14-2 outputs a normal signal as an output signal (e), and the reference potential to transmit an alarm information signal is set with resistors 12, 13 and 16, 17. The two output signals (d) and (e) are added at an OR gate 18-1, and an added signal (f) is inputted to the clock terminal of flip-flops FF19-1 and 19-2. At the terminal Q of the FF19-1, a signal (g) frequency dividing the signal (f) to halves is obtained, and this signal (g) is applied to the terminal J of the FF19-2 through a delay circuit consisting of a resistor 21 and a capacitor 22. Thus, the alarm information signal stable from a low to high frequency band is obtained.
JP7713380A 1980-06-10 1980-06-10 Level detecting circuit Pending JPS573457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7713380A JPS573457A (en) 1980-06-10 1980-06-10 Level detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7713380A JPS573457A (en) 1980-06-10 1980-06-10 Level detecting circuit

Publications (1)

Publication Number Publication Date
JPS573457A true JPS573457A (en) 1982-01-08

Family

ID=13625298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7713380A Pending JPS573457A (en) 1980-06-10 1980-06-10 Level detecting circuit

Country Status (1)

Country Link
JP (1) JPS573457A (en)

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