JPS5730414A - Offset automatic compensating system - Google Patents

Offset automatic compensating system

Info

Publication number
JPS5730414A
JPS5730414A JP10459180A JP10459180A JPS5730414A JP S5730414 A JPS5730414 A JP S5730414A JP 10459180 A JP10459180 A JP 10459180A JP 10459180 A JP10459180 A JP 10459180A JP S5730414 A JPS5730414 A JP S5730414A
Authority
JP
Japan
Prior art keywords
current
current source
voltage
memory
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10459180A
Other languages
Japanese (ja)
Inventor
Kiyoshi Takayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10459180A priority Critical patent/JPS5730414A/en
Publication of JPS5730414A publication Critical patent/JPS5730414A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To prevent the production of offset current, by automatically balancing the current of the current source with a compensation circuit. CONSTITUTION:In the test mode, switching circuits SW2, SW4 are at off-state and SW1, SW3 are at no-stage, the current I1 of a current source 3 flows to a resistor 10 and the SW3 via the SW1, and the latter is the current I2 of a current source 4. In this case, if the currents I1, I2 are unbalanced, the current IR of the difference flows to the resistor 10 to generate a voltage VR. This voltage VRis detected at a voltage comparator 11 and after the output voltage Vt is converted into a digital signal ADt at an AD converter 12, it is outputted to a memory 13. The memory 13 produces an analog signal Mt corresponding to the ADt adjustment is made so that the current I2 of the current source 4 is equal to the I1. When the I1 is equal to the I2, the IR is zero and the VR=0 volt. A 0V detector 14 detects this state to produce a control signal Vs and to keep the memory 13 to the state.
JP10459180A 1980-07-30 1980-07-30 Offset automatic compensating system Pending JPS5730414A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10459180A JPS5730414A (en) 1980-07-30 1980-07-30 Offset automatic compensating system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10459180A JPS5730414A (en) 1980-07-30 1980-07-30 Offset automatic compensating system

Publications (1)

Publication Number Publication Date
JPS5730414A true JPS5730414A (en) 1982-02-18

Family

ID=14384669

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10459180A Pending JPS5730414A (en) 1980-07-30 1980-07-30 Offset automatic compensating system

Country Status (1)

Country Link
JP (1) JPS5730414A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6152015A (en) * 1984-08-22 1986-03-14 Nec Corp Loop filter
JPS61182319A (en) * 1985-02-01 1986-08-15 アドバンスト・マイクロ・デイバイシズ・インコーポレーテツド Load pump unit
JPS6249719A (en) * 1985-08-29 1987-03-04 Matsushita Electric Ind Co Ltd Phase comparator
JPS6257317A (en) * 1985-09-06 1987-03-13 Hitachi Ltd Clock circuit
JPS63120157A (en) * 1986-11-06 1988-05-24 平岡工業株式会社 Lace embroidering machine
JPH02230821A (en) * 1989-03-03 1990-09-13 Hitachi Ltd Clock generator and information processing system using the same
JPH0429412A (en) * 1990-05-23 1992-01-31 Matsushita Electric Ind Co Ltd Phase comparator
JP2000196442A (en) * 1998-12-22 2000-07-14 Nokia Mobile Phones Ltd Method for balancing output current of charge pump, configuration of charge pump and radio communication unit
JP2009239526A (en) * 2008-03-26 2009-10-15 Sanyo Electric Co Ltd Phase synchronization circuit
JP2010103707A (en) * 2008-10-22 2010-05-06 Canon Inc Charge pumping circuit and clock generator
JP2015516133A (en) * 2012-05-10 2015-06-04 サムスン エレクトロニクス カンパニー リミテッド Transceiver using phase-locked loop switching and phase noise enhancement techniques

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6152015A (en) * 1984-08-22 1986-03-14 Nec Corp Loop filter
JPS61182319A (en) * 1985-02-01 1986-08-15 アドバンスト・マイクロ・デイバイシズ・インコーポレーテツド Load pump unit
JPS6249719A (en) * 1985-08-29 1987-03-04 Matsushita Electric Ind Co Ltd Phase comparator
JPS6257317A (en) * 1985-09-06 1987-03-13 Hitachi Ltd Clock circuit
JPH0260781B2 (en) * 1986-11-06 1990-12-18 Hiraoka Kogyo Kk
JPS63120157A (en) * 1986-11-06 1988-05-24 平岡工業株式会社 Lace embroidering machine
JPH02230821A (en) * 1989-03-03 1990-09-13 Hitachi Ltd Clock generator and information processing system using the same
JPH0429412A (en) * 1990-05-23 1992-01-31 Matsushita Electric Ind Co Ltd Phase comparator
JP2000196442A (en) * 1998-12-22 2000-07-14 Nokia Mobile Phones Ltd Method for balancing output current of charge pump, configuration of charge pump and radio communication unit
JP2009239526A (en) * 2008-03-26 2009-10-15 Sanyo Electric Co Ltd Phase synchronization circuit
JP2010103707A (en) * 2008-10-22 2010-05-06 Canon Inc Charge pumping circuit and clock generator
JP2015516133A (en) * 2012-05-10 2015-06-04 サムスン エレクトロニクス カンパニー リミテッド Transceiver using phase-locked loop switching and phase noise enhancement techniques
US9935666B2 (en) 2012-05-10 2018-04-03 Samsung Electronics Co., Ltd. Transceiver using technique for improvement of phase noise and switching of phase lock loop (PLL)

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