GB2215931A

GB2215931A - Amplifying devices

Info

Publication number: GB2215931A
Application number: GB8806779A
Authority: GB
Inventors: Richard Michael Kerslake
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 1988-03-22
Filing date: 1988-03-22
Publication date: 1989-09-27
Also published as: GB8806779D0

Abstract

In an amplifying device e.g. an amplifier or comparator, an input offset of a differential input circuit 5-12 is reduced by temporarily operating switches 3, 4 to apply the same potential to the inputs of 5, 6 and by activating an offset voltage adjustment circuit 15, 19, R1-RN-1; T1-TN to adjust the balance of the input circuit in steps until the output signal at 13 is less than a predetermined small value or changes in polarity, the setting of the adjustment circuit being maintained thereafter during normal operation of the device. A gate 15 is enabled by outputs from 12, 18 to pass clock pulses to a counter 19 whose output causes an appropriate one of transistors T1-TN to conduct to apply different shunt resistors across 9, 11 until the change in output at 13 blocks gate 15. The adjustment may be made on power-up and periodically. Only one of resistors 9, 11 may be variably shunted by the adjustment circuit. The counter may be an up-down counter. <IMAGE>

Description

IMRPOVEMENTS IN OR RELATING TO AMPLIFYING DEVICES This invention relates to amplifying devices such as amplifiers and comparators, and especially to such devices as have differential input terminals.

A particular problem which arises in operational amplifiers and comparators is the presence of input offset voltage errors which result in the device behaving as if it had a potential difference applied to its inputs which differed from that actually present. Such voltage errors can give rise to errors in analogue to digital converting circuits, for example, or in other applications where exact equality between two voltages is to be detected. Even when the amplifier is constructed as an integrated circuit and the differential inputs are connected to the control electrodes of an input pair of supposedly identical transistors, such errors still occur because of small differences between the pair of transistors.

Several techniques have been developed to reduce the offset voltage errors, for example, the so-called "zenerzapping" process of adding progressively increasing corrections to the input circuits which are applied to an integrated circuit amplifier or comparator in the final stages of manufacture, and chopper stabilisation using external components to store a measure of the offset voltage and applying it in a compensating manner to the amplifier or comparator. It is clearly disadvantageous to be required to provide external components additional to the amplifier or comparator as in the case of chopper stabilisation. With the zener-zapping technique, since the adjustment is performed before the device is packaged and the thermal and mechanical stresses applied to the device during packaging can upset the correction applied to the device, the correction may not be of high accuracy.

It is an object of the present invention to provide an improved method of compensating for the offset voltage of an amplifier or comparator in which the above disadvantages are substantially avoided.

According to a first aspect of the present invention there is provided an amplifying device having a differential input circuit with two inputs connected to two input terminals respectively for receiving input signals for amplification with inversion and for amplification without inversion, and an output circuit connected to receive a drive signal from the input circuit so as to produce, in use, an output signal at an output terminal, characterised in that the device also includes a switch means for applying the same potential to the two inputs, an offset voltage adjustment circuit effective to adjust the balance of the input circuit progressively in steps in response to the output signal until the output signal is less than a predetermined small value, and means for temporarily operating the switch means and for activating the offset voltage adjustment circuit while the switch means are operated, the setting of the offset voltage adjustment circuit being maintained after the termination of the operation of the switch means so as to maintain the offset voltage adjustment of the input circuit.

The offset voltage adjustment circuit may include a clock pulse generator, counting means connected to receive pulses from the clock pulse generator and means responsive to the output of the counting means to apply a corresponding voltage offset to the input circuit.

The offset voltage adjustment circuit may otherwise comprise an astable ring counter circuit arranged to apply a progressively changing voltage offset to the input circuit.

The switch means may be arranged simply to connect the two input terminals together; this is satisfactory provided that at least one of the input signals applied to the terminals is at high impedance. The switch means may otherwise be arranged to disconnect the two inputs to the differential input circuit from the two input terminals.

Additionally the switch means may connect both inputs to the differential input circuit to an intermdiate voltage.

The device may include a second switch means disconnecting the output circuit from the output terminal, to be operated whenever the first-mentioned switch means is operated. Such a second switch means will prevent any following circuit connected to the output terminal of the device from influencing the adjustment of the offset voltage.

The counting means may be a multi-stage binary counter the stages of which are connected to switch into circuit binary weighted resistors or binary weighted current sources for effecting the offset voltage adjustment.

The counting means may alternatively be a stepping counter or a shift register containing a single "1" bit starting from a datum position and being stepped along with each clock pulse. The direction of stepping may be dependent on the polarity of the amplifier output. The stages of the shift register are connected to switch into circuit resistors or current sources of progressively increasing values.

The counting means may be unidirectional if the input circuit is designed to have a built-in offset of known polarity. Alternatively, the counting means may be bidirectional and arranged to count in a direction such as to tend to reduce the offset of the input circuit.

The amplifying device may be an operational amplifier and it may be constructed as an integrated circuit.

Alternatively, the device may be an amplifier forming part of a linear integrated circuit for performing some more complicated function or functions than amplification. A comparator is a high gain amplifier with differential inputs, of which the output voltage switches between digital logic voltage levels; an amplifying device according to the invention may be a comparator.

According to a second aspect of the present invention there is provided a method of compensating the offset of an amplifying device having differential input terminals in which stepwise progressively changing offset correction is applied to the device in response to an output signal of the device while the input terminals both receive the same voltage, the stepping of the correction being terminated and the correction value reached being retained when the output of the device switches in polarity.

The changing of the offset correction may involve generating a succession of clock pulses, counting those clock plulses and producing the correction in response to the total number of clock pulses counted.

The method may include connecting the input terminals to the same predetermined voltage. The output of the device may be disconnected from a following circuit while the correction is being determined, so that the following circuit cannot influence the correction.

In order that the invention may be readily carried into effect an embodiment of it together with some modifications will now be described with reference to the accompanying drawings, of which: FIGURE 1 is a circuit diagram partly in block form of the embodiment of the invention; FIGURE 2 shows a modified form of part of the embodiment of Figure 1; and FIGURE 3 shows a modified form of another part of the embodiment of Figure 2.

Figure 1 shows an amplifier having two differential input terminals 1 and 2 connected through switches 3 and 4 respectively to the gates of MOS transistors 5 and 6. The sources of the transistors 5 and 6 are connected together and through a current source 7 to a supply conductor 8. The drain of the transistor 5 is connected through a resistor 9 to a supply conductor 10, and the drain of the transistor 6 is connected through a resistor 11 to the conductor 10. The drains of the transistors 5 and 6 are interconnected by a series chain of resistors R1, R2, ... RN+1, of which the N intermediate junctions are connected to the conductor 10 through the source/drain paths of a number N of MOS transistors T1, T2, ... TN respectively.

The drains of the transistors 5 and 6 are respectively connected to the non-inverting and inverting inputs of an amplifier 12, the output of-which is connected through a switch 13 to an output terminal 14. The design and construction of the amplifier 12 are not of significance to the embodiment of the invention provided that the gain of the amplifier 12 is sufficiently high for the device to operate as described below. The output of the amplifier 12 is also connected to an input of a gate 15, another input of which is connected to receive pulses from a clock pulse generator 16, and a third input is connected through a conductor 17 to a control circuit 18. The output of the gate 15 is applied to the input, of an N-bit counter 19 having a reset input 20 and N outputs connected respectively to the gates G1, G2, ... GN of the transistors T1, T2, ... TN respectively.

The switches 3 and 4 have a second position in which the gates of the transistors 5 and 6 are connected together and to a junction point 21 between resistors 22 and 23 connected in series between the conductors 8 and 10. The switches 3, 4 and 13, which for simplicity in the drawing are shown as mechanical switches, would in practice be electronic switches able to transmit signal voltages without significant distortion. The switches 3, 4 and 13 are controlled by the control unit 18 and these controls are indicated by the broken lines 24 and 25.

In the operation of the embodiment shown in Figure 1, when the power supply is first applied to the circuit, the control unit 18 moves the switches 3, 4 and 13 to the positions shown in Figure 1. With the switches 3 and 4 in this position, the gates of the transistors 5 and 6 receive the same voltage, that at the point 21 which is intermediate between the voltages of the conductors 8 and 10. The voltage on the conductor 8 is VCC (say, +12 volts) and that on the conductor 10 VEE (say, 0 volts). The counter 19 is reset to an initial state by a signal sent from the control unit 18 to the reset input 20. Also at this time the control unit 18 applies a signal along the conductor 17 to open the gate 15.

The values of the drain resistors 9 and 11 of the transistors 5 and 6 are the same but the conduction of the transistor T1 in response to the output of the counter 19 in its initial state causes the total drain load resistance of the transistor 5 to be lower than the total drain load resistance of the transistor 6 so as to provide an offset of known sense between the voltages on the drains of those transistors. The difference between these voltages is amplified by the amplifier 12 and appears at its output as a maximum positive or a maximum negative voltage depending on the design of the circuit. Assume that the output voltage of the amplifier 12 is negative at this time.The gate 15 responds to the output voltage from the amplifier 12 to permit the passage of clock pulses from the generator 16 so as to start the counter 19 counting up. As the number in the counter 19 increases so the gates G1, G2 are powered in succession, turning on the transistors T1, T2, etc. one after the other. At any time only one of the transistors T1, T2, ... TN is conducting. As the total in the counter 19 is increased so the junction of the resistor chain R1, R2, ... RN+1, which is connected to the conductor 10 through one of the transistors T moves from left to right in Figure 1 and the drain load resistance of the transistor 5 increases in value whilst the drain load resistance of the transistor 6 decreases in value.When the relationship between the two drain resistors has changed sufficiently just to overcompensate for the offset voltage error between the two transistors 5 and 6, the output voltage of the amplifier 12 switches suddenly from maximum negative to maximum positive voltage. This change in the output of the amplifier 12 closes the gate 15 so that no more clock pulses can be applied to the counter 19. In this state the counter 19 retains the state which it has reached and maintains the appropriate one of the transistors T1, T2, TN conducting, so providing the optimum offset voltage compensation for the device.The control unit 18, which also receives the output of the amplifier 12, responds to the change in polarity of the output of the amplifier and operates the switches 3, 4 and 13 so that the input terminals 1 and 2 are respectively connected to the gates of the transistors 5 and 6 and the output of the amplifier 12 is connected to the output terminal 14, thereby rendering the device ready for use.

The transistors 5 and 6, and T1, ... TN may be of either polarity. They may also be bipolar transistors instead of the MOS transistors described above.

If the embodiment shown in Figure 1 were a comparator the output voltage of the amplifier 12 would be arranged to switch between voltage levels corresponding to original logic levels.

As described above, the offset voltage compensation routine is performed every time the device is switched on the control unit 18 responding to the power-up transient. In an alternative arrangement the control unit 18 could be caused to perform the routine periodically whilst the device is in operation.

The switches 3, 4 and 13 are operated whilst the offset voltage compensation routine is being performed to isolate the device from the loadings of the external circuits to which it is connected at the time. The switches 3 and 4 may be replaced by a single switch connecting the inputs of the device together; one at least of the input voltages to the device should be supplied at high impedance in this case to avoid excessive loadings on the external circuits. The switch 3 may be omitted if the following circuit cannot influence the output voltage of the device.

Figure 2 shows a modification to the circuit shown in Figure 1 in which the transistors T1, T2, ... TN are connected in series with respective resistors rl, r2, ..., rN between a supply conductor S and another conductor C connected to the drain of one of the transistors 5 and 6.

Depending on the polarities of the transistors the supply conductors may be either one of the conductors 8 and 10. In this case as the counter 19 counts up so a progressively increasing current is applied to the drain resistor of only one of the transistors 5 and 6, but the operation of the circuit is otherwise as described above with reference to Figure 1. The input circuit of the device will need a builtin offset of predetermined polarity in this case to ensure that the adjustment will pass through the zero offset position.

In the modification described with reference to Figure 2, it is necessary for the differential input circuit provided by the transistors 5 and 6 to have a built in imbalance so that the offset voltage is of a predetermined sense, and correction of the imbalance is performed by progressively changing the relationship between the drain resistors until a slight imbalance in the opposite sense is achieved. In another arrangement, the counter is an up/down counter and responds to the polarity of the output of the amplifier 12 to select the direction of counting. An example of this modification is shown in Figure 3.

In the modification shown in Figure 3 the output of the amplifier 12 is applied to two detectors 30 and 31, which respectively respond to the output when it is positive and when it is negative. The detectors are connected to an up/down counter 32 which replaces the counter 19 of Figure 1, the detectors 30 and 31 determining the direction of counting of the counter. Other outputs from the detectors 30 and 31 are applied to a polarity changeover detector 33. In an alternative construction, the output of the amplifier 12 is applied directly to the changeover detector 33. The clock pulse generator 16 is connected to an input of the gate 15 in the same way as is shown in Figure 1 so that when the gate 15 is open clock pulses from the clock 16 are applied to the counter 32. The changeover detector 33 has an output which controls the gate 15, closing the gate when a change occurs in the polarity of the output from the amplifier 12. The counter 32 has a reset input 34 which sets the counter to an initial intermediate state from which it can count up or down as required.

The operation of the circuit of Figure 3 is substantially the same as the operation of the counter 19 as described above with reference to Figure 1, except that the direction of counting is dependent on the polarity of the output of the amplifier 12 and continues until a change in the polarity of the output occurs and is detected by the changeover detector 33.

The accuracy of the offset compensation depends on the number of steps in the adjustment that can be accommodated, which in turn depends on the number of stages of the counter. At least some of the semiconductor bar area needed for the compensation circuitry may be provided by that released by the removal of the zener-zap trim pads (where such were provided) and by the use of smaller input transistors in place of the large cross-coupled common centroid pairs of transistors which are normally used to minimise the offset voltage.

Claims

1. An amplifying device having a differential input circuit with two inputs connected to two input terminals respectively for receiving input signals for amplification with inversion and for amplification without inversion, and an output circuit connected to receive a drive signal from the input circuit so as to produce, in use, an output signal at an output terminal, characterised in that the device also includes a switch means for applying the same potential to the two inputs, an offset voltage adjustment circuit effective to adjust the balance of the input circuit progressively in steps in response to the output signal until the output signal is less than a predetermined small value, and means for temporarily operating the switch means and for activating the offset voltage adjustment circuit while the switch means are operated, the setting of the offset voltage adjustment circuit being maintained after the termination of the operation of the switch means so as to maintain the offset voltage adjustment of the input circuit.

2. A device according to Claim 1, characterised in that the offset voltage adjustment circuit includes a clock pulse generator, counting means connected to receive pulses from the clock pulse generator when the offset voltage adjustment circuit is activated and the output signal is greater than the predetermined small value, and means responsive to the output of the counting means to apply a corresponding voltage offset to the input circuit.

3. A device according to Claim 1, characterised in that the offset voltage adjustment circuit includes an astable ring counter circuit which operates when the offset voltage adjustment circuit is activated and the output signal is greater than the predetermined small value, and means responsive to the output of the counter circuit for applying a progressively changing voltage offset to the input circuit.

4. A device according to Claim 2 characterised in that the counting means is a multi-stage binary counter and the responsive means includes binary weighted resistors or binary weighted current sources connected to the input circuit by switching elements respectively controlled by the stages of the binary counter.

5. A device according to Claim 2 characterised in that the counting means is a stepping counter or a shift register containing a single "1" bit, and the responsive

means includes resistors or current sources/progrcssively increasing values connected to the input circuit by switching elements respectively controlled by the stages of the stepping counter or shift register.

6. A device according to any one of Claims 2 to 5, characterised in that the input circuit has a built-in offset and that the counting means or counter circuit is unidirectional.

7. A device according to any one of Claims 2 to 5 characterised in that the counting means or counter circuit is bidirectional and is responsive to the polarity of the output signal to count in a direction such as to tend to reduce the offset of the input circuit.

8. A device according to any one of the preceding claims, characterised in that the switch means is arranged to connect the inputs of the differential input circuit together.

9. A device according to Claim 8 characterised in that the switch means additionally disconnects the inputs of the differential input circuit from the input terminals when it connects the inputs together.

10. A device according to Claim 9 characterised in that the switch means additionally connects the inputs of the differential input circuit to an intermediate voltage when it connects the inputs together.

11. A device according to any one of the preceding claims characterised in that a further switch element is provided effective to disconnect the output circuit from the output terminal whenever the switch means is operated.

12. A device according to any one of the preceding claims characterised in that means is provided for operating the switch means in response to a power-up transient.

13. A device according to Claim 12 characterised in that the means for operating the switch means periodically operates the switch means during the operation of the device.

14. An amplifying device substantially as described herein and as illustrated by Figure 1 of the accompanying drawings, or modified as described with reference to Figure 2 and/or Figure 3 of the accompanying drawings.

15. An integrated circuit including a device according to any one of the preceding claims.

16. A method of compensating the offset of an amplifying device having differential input terminals in which stepwise progressively changing offset correction is applied to the device in response to an output signal of the device while the input terminals both receive the same voltage, the stepping of the correction being terminated and the correction value reached being retained when the output of the device switches in polarity.

17. A method according to Claim 16 characterised in that the stepwise progressively changing offset correction is produced by generating a succession of clock pulses, counting the clock pulses and producing the correction in response to the number of clock pulses counted.

18. A method according to Claim 16 or Claim 17 characterised by connecting the both input terminals to the same source of a predetermined voltage so that they receive the same voltage.

19. A method according to Claim 16, Claim 17 or Claim 18 characterised by disconnecting the output of the device from the following circuit while the correction is being -determined.

20. A method of compensating the offset of an amplifying device having differential input terminals substantially as described herein and as illustrated by Figure 1 of the accompanying drawings or modified as illustrated by Figure 2 and Figure 3 of the accompanying drawings.