JPS5728128B2 - - Google Patents

Info

Publication number
JPS5728128B2
JPS5728128B2 JP6870178A JP6870178A JPS5728128B2 JP S5728128 B2 JPS5728128 B2 JP S5728128B2 JP 6870178 A JP6870178 A JP 6870178A JP 6870178 A JP6870178 A JP 6870178A JP S5728128 B2 JPS5728128 B2 JP S5728128B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP6870178A
Other languages
Japanese (ja)
Other versions
JPS54159831A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6870178A priority Critical patent/JPS54159831A/en
Publication of JPS54159831A publication Critical patent/JPS54159831A/en
Publication of JPS5728128B2 publication Critical patent/JPS5728128B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/3816—Accepting numbers of variable word length
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/481—Counters performing arithmetic operations
JP6870178A 1978-06-07 1978-06-07 Adder and subtractor for numbers different in data length using counter circuit Granted JPS54159831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6870178A JPS54159831A (en) 1978-06-07 1978-06-07 Adder and subtractor for numbers different in data length using counter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6870178A JPS54159831A (en) 1978-06-07 1978-06-07 Adder and subtractor for numbers different in data length using counter circuit

Publications (2)

Publication Number Publication Date
JPS54159831A JPS54159831A (en) 1979-12-18
JPS5728128B2 true JPS5728128B2 (en) 1982-06-15

Family

ID=13381325

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6870178A Granted JPS54159831A (en) 1978-06-07 1978-06-07 Adder and subtractor for numbers different in data length using counter circuit

Country Status (1)

Country Link
JP (1) JPS54159831A (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4203157A (en) * 1978-09-05 1980-05-13 Motorola, Inc. Carry anticipator circuit and method
JPS56147047A (en) * 1980-04-18 1981-11-14 Hitachi Ltd Bit division type adder
JPS58182754A (en) * 1982-04-19 1983-10-25 Hitachi Ltd Arithmetic processor
JP2522239B2 (en) * 1984-03-08 1996-08-07 ソニー株式会社 Digital signal processor
JPS617945A (en) * 1984-06-22 1986-01-14 Usac Electronics Ind Co Ltd Effective address calculating system
US4685078A (en) * 1984-10-31 1987-08-04 International Business Machines Corporation Dual incrementor
JPS61250733A (en) * 1985-04-30 1986-11-07 Fujitsu Ltd Addition and subtraction circuit
JP2575620B2 (en) * 1985-05-23 1997-01-29 富士ゼロックス株式会社 Data processing device
JPS62111362A (en) * 1985-11-08 1987-05-22 Matsushita Electric Ind Co Ltd Data processor
JPS62269228A (en) * 1986-05-16 1987-11-21 Matsushita Electric Ind Co Ltd Arithmetic and logic unit
JPS6491228A (en) * 1987-09-30 1989-04-10 Takeshi Sakamura Data processor
JPH05216624A (en) * 1992-02-03 1993-08-27 Mitsubishi Electric Corp Arithmetic unit

Also Published As

Publication number Publication date
JPS54159831A (en) 1979-12-18

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