JPS617945A - Effective address calculating system - Google Patents

Abstract

PURPOSE:To shorten remarkably the calculation time of an effective address by dividing the effective address into the lower part being equal to an operating bit width and the residual upper part, and calculating the lower part and the upper part by an ALU and a reversible counter, respectively. CONSTITUTION:When calculating an effective address, an enable signal 14 is set to ''1'', and a selector circuit 12 is made operable. An up/down signal switches the circuit 12 to a C side when an index code is ''0'', and to an N side when said code is ''1''. This signal is applied to a reversible counter at the same time, and an increment operation and a decrement operation are executed, at the time of ''0'' and ''1'', respectively. As for the counter 13, the upper 8-bit of a base register is set in advance. An arithmetic unit ALU11 calculates the lower 16-bit of the effective address. When a carry C is applied from the ALU11, the counter 13 adds ''1'' to a value of the upper 8-bit of the base register, and subtracts ''1'' when a negative N is applied. In such a way, the lower 16-bit of the effective address is obtained from the ALU11, and the upper 8-bit of the effective address is obtained from the counter 13.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an effective address calculation method in a data processing device, and in particular to a method for quickly calculating an effective address whose bit width is larger than the parallel operation width of a processor. Regarding the method.

[Conventional technology]

Conventionally, for example, in a CPU with 16-bit parallel processing, AL
Since the U (arithmetic unit) is 16 bits wide, when calculating a 24-bit effective address in indirect format with index and displacement, the effective address is divided into the lower 16 bits and the upper 8 bits and calculated twice. Normally, the calculation is divided into two parts, otherwise it would be necessary to use a CPU with a 24-bit width.

FIG. 2 is an explanatory diagram of a conventional method in which effective address calculation is performed separately. In the figure, 1 is the instruction word, 2 is the displacement, 3 is the two-word pace register, and 4 is the instruction word.
is the index register, 5 is the first calculation process,
6, 7.8 are registers, and 9 is the second calculation process.

In the first calculation process 5, the lower 16 bits of the pace register 3, the 16 bits of the index register 4, and the 12 bits of the displacement 2 are added, and the result is the lower 16 bits of the effective address.

Generates a carry (carry) C or negative (borrow) N to the upper digit. Negative N is output when the sign of the index is negative, the calculation result of the lower part of the effective address is negative, and a borrow occurs in the upper part. The lower part of the effective address is stored in register 6, and the C/N is stored in register 7.

In the second calculation process 9, the upper 8 bits of the pace register 3 and the C/N of the register 7 are calculated.

If C=1, the upper 8 bits of the pace register are filled],
Conversely, if L and N=1, they are incremented by -1. The result is stored in register 8 as the upper part of the effective address. Once the effective addresses are obtained in registers 6 and 8 in this way, they are output for memory access.

[Problem that the invention seeks to solve]

In the conventional method of calculating one effective address in two steps, it takes two machine cycles to add the ALU, one machine cycle to check the sign of the index register, and one machine cycle to check the sign of the index register.
Since one machine cycle is used to temporarily store the output of U in the register, a total of seven machine cycles are required, resulting in a problem of long calculation time.

On the other hand.

If the operation bit width of the ALU was configured to match the focus width of the effective address, the amount of hardware would increase, resulting in an increase in price and other problems.

[Means for solving problems]

In the present invention, it is possible to calculate the effective address only once, and therefore, the calculation of the upper part of the effective address is performed without the carry (carry) that occurs in the calculation of the lower part.
or +1 or -1 to handle negative (borrowed digits)
Focusing on the fact that it only requires calculation of Something, specifically.

An ALU with carry and negative outputs.

In a data processing device having an effective address larger than the operational bit width of the ALU, a reversible counter coupled to the carry and negative outputs of the ALU is provided, and the counter is incremented by the carry output and decremented by the negative output. furthermore, the effective address has a lower part equal to the operation bit width of the ALU,
The effective address is divided into the remaining upper part, the lower part of the effective address is calculated by the ALU, and the upper part is calculated by the reversible counter.

〔Example〕

The details of the present invention will be explained below based on examples.

FIG. 1 is an explanatory diagram showing the principle of the present invention. In the figure, il is a 16-bit ALU with N (negative) and C (carry) outputs, 12 is a selector circuit, and 13 is an 8-bit ALU.
The bit reversible counter ADRH, 14 is an enable signal, and 15 is an up/down signal.

Enable signal 14 is used during effective address calculation.

It is set to "1" and the selector circuit 12 is enabled.

The up/down signal is determined based on the sign of the index, and when it is "0", the selector circuit 12 is switched to the C side, and when it is "1", it is switched to the N side.

This up/down signal is simultaneously added to the reversible counter 13, and when it is 0'', it is incremented (step up).
When the flag is "1", a decrement (step down) operation is performed.

The upper eight bits of the pace register are set in advance in the reversible counter 13. ALUI 1 is the lower 1 of the effective address
When 6 bits are calculated and a carry C or negative N occurs as a result, the reversible counter 1 passes through the selector circuit 12.
3.

The reversible counter 13 receives a carry C from the ALU II, that is, when a one-digit increment occurs in the calculation of the lower part of the effective address in the ALU.

Step up, that is, add 1 to the value of the upper 8 bits of the pace register. On the other hand, negative N from ALUII
is applied, that is, the sign of the index is “−”
”, when a digit is borrowed, the reversible counter 13 is
Step down, that is, subtract 1 from the value of the upper 8 bits of the pace register.

In this way, from ALUII to the lower 1 of the effective address
6 bits are obtained, and the upper 8 bits of the effective address are obtained from the reversible counter 13.

FIG. 3 is a block diagram of one embodiment of the present invention.

In the figure, 16 is a memory, 17 is a read data register RDR, and 18 is a register D that stores a 12-bit displacement direct value.

19 is register B specifying the pace register, 20
is register X that specifies the index register.

21 is a general-purpose register, 22 is an index register with 16 pins each, 23 is a heath register with 24 bits each, 2
4 is a selector, 25 is a 16-bit ALU, 26 is an accumulator ACC, 27 is an address register ADRL that stores the lower 16 bits of the effective address, and 28 is the upper 8 effective addresses that are constructed of an 8-bit reversible counter according to the present invention. Bit address register ADRH, 29 indicates a 7' address bus.

FIG. 4 shows the basic control operations using flows ① to ②.

■ First, select the pace register 23, and input its upper 8 bits to the selector 24. It is set in the address register ADRH 28 of the reversible counter via the ALU 25.

■ Select the index register 22, read its 16 bits, and select the selector 24. It is set to accumulator ACC26 via ALU25. At this time, if the index value is negative, N-"l" is output from the ALU 25 and the address register ADRH 28 is decremented.

(2) The ALU 25 adds the index value of the accumulator ACC26 and the 12-bit displacement value of the register D18, and if there is a carry C, the ADRH 28 is incremented. The addition result of ALU25 is ACC2
6.

(2) Finally, the ALU 25 adds the value of the ACC 26 and the lower 16 bits of the pace register 23, and if there is a carry C, the ADRH 28 is incremented. The addition result of the ALU 25 is stored in the address register A and DRL 27.

In this way, address registers ADRL27, AD
The lower 16 bits and upper 8 bits of the effective address are generated in the RH 28 and output to the address bus 29, respectively.

In this embodiment, effective address calculation could be executed in 4 machine cycles.

The present invention can be applied to any case where the focus width of the effective address is larger than the bit width of the ALU.

〔Effect of the invention〕

As described above, according to the present invention, effective address calculation can be executed in fewer machine cycles with only a slight increase in hardware, and the calculation time is significantly reduced compared to the case where calculation is performed in two steps. can be shortened.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is an explanatory diagram of a conventional system, and FIG. 3 is a configuration diagram of one embodiment of the present invention. FIG. 4 is a control flow diagram of this embodiment. In the figure, 11 is a 16-biso I ALU, 12 is a selector circuit, 13 is a reversible counter, 14 is an enable signal, and 15 is a reversible counter.
are up/down signals. Patent applicant: Usatsuk Electronic Industry Co., Ltd. Representative Patent Attorney Fumihiro Hase (2 others) Said II! 1 year old 2 ffl.

Claims (1)

[Claims] An ALU with carry and negative outputs and
In a data processing device having an effective address larger than the arithmetic bit width of the LU, a reversible counter coupled to the carry and negative outputs of the ALU is provided, and is incremented by the carry output and decremented by the negative output. further divide the effective address into a lower part equal to the operation bit width of the ALU and the remaining upper part, calculate the lower part of the effective address by the ALU, and calculate the upper part by the reversible counter. An effective address calculation method characterized by: