JPS5727558B2 - - Google Patents
Info
- Publication number
- JPS5727558B2 JPS5727558B2 JP11026977A JP11026977A JPS5727558B2 JP S5727558 B2 JPS5727558 B2 JP S5727558B2 JP 11026977 A JP11026977 A JP 11026977A JP 11026977 A JP11026977 A JP 11026977A JP S5727558 B2 JPS5727558 B2 JP S5727558B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
Landscapes
- Read Only Memory (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11026977A JPS5443633A (en) | 1977-09-13 | 1977-09-13 | Memory erasing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11026977A JPS5443633A (en) | 1977-09-13 | 1977-09-13 | Memory erasing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5443633A JPS5443633A (en) | 1979-04-06 |
| JPS5727558B2 true JPS5727558B2 (ja) | 1982-06-11 |
Family
ID=14531393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11026977A Granted JPS5443633A (en) | 1977-09-13 | 1977-09-13 | Memory erasing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5443633A (ja) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6315615Y2 (ja) * | 1986-12-25 | 1988-05-02 | ||
| JPH0381028B2 (ja) * | 1982-11-18 | 1991-12-26 | Hiroshi Teramachi |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4412309A (en) * | 1981-09-28 | 1983-10-25 | Motorola, Inc. | EEPROM With bulk zero program capability |
| US4628487A (en) * | 1984-08-14 | 1986-12-09 | Texas Instruments Incorporated | Dual slope, feedback controlled, EEPROM programming |
| JPH02126498A (ja) * | 1988-07-08 | 1990-05-15 | Hitachi Ltd | 不揮発性半導体記憶装置 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4846230A (ja) * | 1971-10-14 | 1973-07-02 |
-
1977
- 1977-09-13 JP JP11026977A patent/JPS5443633A/ja active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4846230A (ja) * | 1971-10-14 | 1973-07-02 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0381028B2 (ja) * | 1982-11-18 | 1991-12-26 | Hiroshi Teramachi | |
| JPS6315615Y2 (ja) * | 1986-12-25 | 1988-05-02 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5443633A (en) | 1979-04-06 |