JPS5727323A - Input and output control device for microprogram control - Google Patents
Input and output control device for microprogram controlInfo
- Publication number
- JPS5727323A JPS5727323A JP10204580A JP10204580A JPS5727323A JP S5727323 A JPS5727323 A JP S5727323A JP 10204580 A JP10204580 A JP 10204580A JP 10204580 A JP10204580 A JP 10204580A JP S5727323 A JPS5727323 A JP S5727323A
- Authority
- JP
- Japan
- Prior art keywords
- upper device
- ram
- microprogram
- input
- data transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To permit operation despite the occurrence of a fault by loading the microprogram transferred from an upper device onto an RAM when the fault occurs in initial program loading processing. CONSTITUTION:An RAM 2 in which microprograms MP are stored, a microprocessor MPU 1 which executes processing based on the contens thereof, a data transfer control part 5 which intermediates data transfer between the same and an upper device and an MP storage device control part 7 are provided. When a fault occurs in the initial loading processing to be carried out via the part 7, the MPU 1 issues an MP request interruption status to the upper device via the part 5, so that the MP transferred from the upper device is loaded onto the RAM 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10204580A JPS5727323A (en) | 1980-07-25 | 1980-07-25 | Input and output control device for microprogram control |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10204580A JPS5727323A (en) | 1980-07-25 | 1980-07-25 | Input and output control device for microprogram control |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5727323A true JPS5727323A (en) | 1982-02-13 |
Family
ID=14316794
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10204580A Pending JPS5727323A (en) | 1980-07-25 | 1980-07-25 | Input and output control device for microprogram control |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5727323A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05128139A (en) * | 1991-11-05 | 1993-05-25 | Oki Electric Ind Co Ltd | Automatic transaction machine |
-
1980
- 1980-07-25 JP JP10204580A patent/JPS5727323A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05128139A (en) * | 1991-11-05 | 1993-05-25 | Oki Electric Ind Co Ltd | Automatic transaction machine |
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