JPS5725044A - Initial microprogram load execution control system - Google Patents
Initial microprogram load execution control systemInfo
- Publication number
- JPS5725044A JPS5725044A JP9874880A JP9874880A JPS5725044A JP S5725044 A JPS5725044 A JP S5725044A JP 9874880 A JP9874880 A JP 9874880A JP 9874880 A JP9874880 A JP 9874880A JP S5725044 A JPS5725044 A JP S5725044A
- Authority
- JP
- Japan
- Prior art keywords
- impl
- signal
- turned
- reset
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/24—Loading of the microprogram
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To elevate a successful probability of IMPL, by generating a signal for instructing the regeneration of an IMPL start signal, when an initial microprogram load (IMPL) has ended in failure. CONSTITUTION:When an IMPL instruction signal 9 is turned on as a result of turn- on of an electric power source, etc. of a data processing equipment, FFs 1, 2 are set, an IMPL start signal 12 is turned on only for a short time, an FF3 is reset, and a counter 4 is cleared. When the IMPL starts, an IMPL start signal 14 is turned on, the FF1 is reset, the signal 12 is turned off, an IMPL successful signal 10 is turned on, and the FF2 is reset. When the execution of IMPL fails, a check signal 16 is turned on and the FF3 is set. In this case, since the FF2 is in a set state, an AND gate 6 is opened, the FF1 is set over again, the signal 12 is restarted, also the counter 4 is operated, the FF2 is held, and this operation is repeated. When the IMPL is successful and the signal 10 is on, or when a count value of the counter 4 attains to a prescribed value, the FF2 is reset, and restart of the IMPL is stopped.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9874880A JPS5725044A (en) | 1980-07-21 | 1980-07-21 | Initial microprogram load execution control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9874880A JPS5725044A (en) | 1980-07-21 | 1980-07-21 | Initial microprogram load execution control system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5725044A true JPS5725044A (en) | 1982-02-09 |
Family
ID=14228082
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9874880A Pending JPS5725044A (en) | 1980-07-21 | 1980-07-21 | Initial microprogram load execution control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5725044A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6162956A (en) * | 1984-09-05 | 1986-03-31 | Hitachi Ltd | Ipl control system of processor |
| JPS6238916A (en) * | 1985-08-14 | 1987-02-19 | Nec Corp | Rise-up system of data processing system |
-
1980
- 1980-07-21 JP JP9874880A patent/JPS5725044A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6162956A (en) * | 1984-09-05 | 1986-03-31 | Hitachi Ltd | Ipl control system of processor |
| JPH0316656B2 (en) * | 1984-09-05 | 1991-03-06 | Hitachi Ltd | |
| JPS6238916A (en) * | 1985-08-14 | 1987-02-19 | Nec Corp | Rise-up system of data processing system |
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