JPS5723219A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5723219A
JPS5723219A JP9724680A JP9724680A JPS5723219A JP S5723219 A JPS5723219 A JP S5723219A JP 9724680 A JP9724680 A JP 9724680A JP 9724680 A JP9724680 A JP 9724680A JP S5723219 A JPS5723219 A JP S5723219A
Authority
JP
Japan
Prior art keywords
layer
aperture
larger
superposed
shallow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9724680A
Other languages
Japanese (ja)
Inventor
Toshiyasu Shimada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9724680A priority Critical patent/JPS5723219A/en
Publication of JPS5723219A publication Critical patent/JPS5723219A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation

Landscapes

  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain a high withstand voltage element by a method wherein an insulating film, having the second aperture which is larger than the first aperture, is superposed on the insulating film having the first aperture and then ion is implanted therein. CONSTITUTION:An N<-> epitaxial layer 11 is superposed on an N type Si substrate 10 and an aperture is provided on an SiO2 film 12. A resist mask 13, having an aperture larger than said apertures, is provided and then B ion is implanted. As a result, a layer 14 is turned to P type, a layer 15 decreases in density and a high resistance is generated, and the layer 14 is surrounded by a shallow N<--> layer 15. Consequently, by the aid of a shallow P-N junction, the percentage of elongation of a depletion layer becomes larger when the radius curvature is enlarged on the side section by the effect of the low density of the N layer 15 and the diode of high withstand voltage can be obtained.
JP9724680A 1980-07-16 1980-07-16 Manufacture of semiconductor device Pending JPS5723219A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9724680A JPS5723219A (en) 1980-07-16 1980-07-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9724680A JPS5723219A (en) 1980-07-16 1980-07-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5723219A true JPS5723219A (en) 1982-02-06

Family

ID=14187223

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9724680A Pending JPS5723219A (en) 1980-07-16 1980-07-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5723219A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4829019A (en) * 1987-05-12 1989-05-09 Texas Instruments Incorporated Method for increasing source/drain to channel stop breakdown and decrease P+/N+ encroachment

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5018176A (en) * 1973-06-20 1975-02-26

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5018176A (en) * 1973-06-20 1975-02-26

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4829019A (en) * 1987-05-12 1989-05-09 Texas Instruments Incorporated Method for increasing source/drain to channel stop breakdown and decrease P+/N+ encroachment

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