JPS57210498A - Data storage controller - Google Patents

Data storage controller

Info

Publication number
JPS57210498A
JPS57210498A JP56094826A JP9482681A JPS57210498A JP S57210498 A JPS57210498 A JP S57210498A JP 56094826 A JP56094826 A JP 56094826A JP 9482681 A JP9482681 A JP 9482681A JP S57210498 A JPS57210498 A JP S57210498A
Authority
JP
Japan
Prior art keywords
data transfer
address
register
supplied
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56094826A
Other languages
Japanese (ja)
Inventor
Toshio Asaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56094826A priority Critical patent/JPS57210498A/en
Publication of JPS57210498A publication Critical patent/JPS57210498A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0763—Error or fault detection not based on redundancy by bit configuration check, e.g. of formats or tags

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To perform error detection during data transfer by providing an end address register which calculates and holds the contents expected numeral of an address register. CONSTITUTION:An address P at the time of the start of data transfer is supplied to an address register 12 and evey time the data transfer is carried out, an arithmetic unit ALU1 specifies an address successively. A counter register 13 is the same. The positive and negative sign code from a sign detecting circuit 14 supplied with information on addition or subtraction are supplied to an arithmetic unit ALU3, which calculates and sets the ending address of transferred data in an ending address register 15. As the data transfer advances, the contents of the register 13 decrease to 0 and an ALU2 sends out 0 to complete the data transfer. At this point of time, the contents of the registers 12 and 15 are compared with each other to detect an error.
JP56094826A 1981-06-19 1981-06-19 Data storage controller Pending JPS57210498A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56094826A JPS57210498A (en) 1981-06-19 1981-06-19 Data storage controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56094826A JPS57210498A (en) 1981-06-19 1981-06-19 Data storage controller

Publications (1)

Publication Number Publication Date
JPS57210498A true JPS57210498A (en) 1982-12-24

Family

ID=14120851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56094826A Pending JPS57210498A (en) 1981-06-19 1981-06-19 Data storage controller

Country Status (1)

Country Link
JP (1) JPS57210498A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58127467U (en) * 1982-02-23 1983-08-29 松下電器産業株式会社 tape cassette
WO1997047115A1 (en) * 1996-06-06 1997-12-11 Advanced Micro Devices, Inc. End of packet detection for storing multiple packets in an sram

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58127467U (en) * 1982-02-23 1983-08-29 松下電器産業株式会社 tape cassette
JPS6317083Y2 (en) * 1982-02-23 1988-05-16
WO1997047115A1 (en) * 1996-06-06 1997-12-11 Advanced Micro Devices, Inc. End of packet detection for storing multiple packets in an sram
US5819113A (en) * 1996-06-06 1998-10-06 Advanced Micro Devices, Inc. Method of identifying end of pocket by writing the address of last data into the first location of the memory

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