JPS57208684A - Buffer recording device - Google Patents

Buffer recording device

Info

Publication number
JPS57208684A
JPS57208684A JP56093040A JP9304081A JPS57208684A JP S57208684 A JPS57208684 A JP S57208684A JP 56093040 A JP56093040 A JP 56093040A JP 9304081 A JP9304081 A JP 9304081A JP S57208684 A JPS57208684 A JP S57208684A
Authority
JP
Japan
Prior art keywords
data
buffer
memory
transferred
given
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56093040A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6136666B2 (cs
Inventor
Koichi Tsukizoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56093040A priority Critical patent/JPS57208684A/ja
Publication of JPS57208684A publication Critical patent/JPS57208684A/ja
Publication of JPS6136666B2 publication Critical patent/JPS6136666B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP56093040A 1981-06-18 1981-06-18 Buffer recording device Granted JPS57208684A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56093040A JPS57208684A (en) 1981-06-18 1981-06-18 Buffer recording device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56093040A JPS57208684A (en) 1981-06-18 1981-06-18 Buffer recording device

Publications (2)

Publication Number Publication Date
JPS57208684A true JPS57208684A (en) 1982-12-21
JPS6136666B2 JPS6136666B2 (cs) 1986-08-19

Family

ID=14071379

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56093040A Granted JPS57208684A (en) 1981-06-18 1981-06-18 Buffer recording device

Country Status (1)

Country Link
JP (1) JPS57208684A (cs)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6168655A (ja) * 1984-09-11 1986-04-09 Fujitsu Ltd バツフアストレ−ジのアクセス方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6168655A (ja) * 1984-09-11 1986-04-09 Fujitsu Ltd バツフアストレ−ジのアクセス方法

Also Published As

Publication number Publication date
JPS6136666B2 (cs) 1986-08-19

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