JPS57206984A - Absolute value circuit - Google Patents
Absolute value circuitInfo
- Publication number
- JPS57206984A JPS57206984A JP10372981A JP10372981A JPS57206984A JP S57206984 A JPS57206984 A JP S57206984A JP 10372981 A JP10372981 A JP 10372981A JP 10372981 A JP10372981 A JP 10372981A JP S57206984 A JPS57206984 A JP S57206984A
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- turned
- signal
- output terminal
- absolute value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
- G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
- G06G7/25—Arrangements for performing computing operations, e.g. operational amplifiers for discontinuous functions, e.g. backlash, dead zone, limiting absolute value or peak value
Abstract
PURPOSE:To simplify the constitution of an absolute value circuit with a reduction of cost, by combining the positive and negative polarity half-wave linear detecting circuits together. CONSTITUTION:The input signal fed to an input terminal 11 has the positive polarity and is accordingly amplified by an inverting amplifier 12 after passing through the resistances R7 and R8 to be turned into the negative polar at the output terminal of the amplifier 12. As a result, the diodes D4 and D3 are turned off and on respectively, and an end of the resistor R8 at the side connected to the amplifier 12 is equivalently earthed. In case the input signal is negative polar, this signal is amplified by the amplifier 12 after passing through the resistances R7 and R8 and turned into a signal of positive polarity at the output terminal of the amplifier 12. Accordingly the diodes D3 and D4 are turned off and on respectively, and no voltage is generated across the resistance R8. Thus no output signal is obtained at the output terminal 13.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10372981A JPS57206984A (en) | 1981-07-02 | 1981-07-02 | Absolute value circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10372981A JPS57206984A (en) | 1981-07-02 | 1981-07-02 | Absolute value circuit |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9202781A Division JPS57208866A (en) | 1981-06-09 | 1981-06-15 | Rectifying time-constant circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57206984A true JPS57206984A (en) | 1982-12-18 |
JPS611795B2 JPS611795B2 (en) | 1986-01-20 |
Family
ID=14361732
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10372981A Granted JPS57206984A (en) | 1981-07-02 | 1981-07-02 | Absolute value circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57206984A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62129660U (en) * | 1986-02-03 | 1987-08-17 |
-
1981
- 1981-07-02 JP JP10372981A patent/JPS57206984A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62129660U (en) * | 1986-02-03 | 1987-08-17 |
Also Published As
Publication number | Publication date |
---|---|
JPS611795B2 (en) | 1986-01-20 |
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