JPS57206945A - Mounting base for input/output module and its connecting structure to parallel bus line - Google Patents

Mounting base for input/output module and its connecting structure to parallel bus line

Info

Publication number
JPS57206945A
JPS57206945A JP56090765A JP9076581A JPS57206945A JP S57206945 A JPS57206945 A JP S57206945A JP 56090765 A JP56090765 A JP 56090765A JP 9076581 A JP9076581 A JP 9076581A JP S57206945 A JPS57206945 A JP S57206945A
Authority
JP
Japan
Prior art keywords
module
input
modules
mounting base
output module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56090765A
Other languages
Japanese (ja)
Inventor
Katsutoshi Kishigami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56090765A priority Critical patent/JPS57206945A/en
Publication of JPS57206945A publication Critical patent/JPS57206945A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE:To improve workability at the time of wiring, maintenance and operation by making the arraying state of signal lines of terminal boards and display lamps in the same input/output modules mounted symmetrically up and down coincide with each other when observing from a certain direction. CONSTITUTION:Input/output modules 1 are constituted fundamentally by the same format and the same kinds of I/O modules are arrayed up and down so as to put a CPU module 5 between the upper and lower modules. In the upper and lower modules, the arraying state of signal lines on terminal boards 2 and display lamps 3 are turned by 180 deg. each other and is not coincident with each other when observing from one way. If I/O numbers in a module connector 4B corresponding to one I/O module B are assigned reversely against that of the module connector 4C of the other I/O module C and, simultaneously, I/O numbers on the terminal board of one I/O module B are assigned in the same direction as that of the other I/O module C, said arraying state can be made to coincide with each other.
JP56090765A 1981-06-15 1981-06-15 Mounting base for input/output module and its connecting structure to parallel bus line Pending JPS57206945A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56090765A JPS57206945A (en) 1981-06-15 1981-06-15 Mounting base for input/output module and its connecting structure to parallel bus line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56090765A JPS57206945A (en) 1981-06-15 1981-06-15 Mounting base for input/output module and its connecting structure to parallel bus line

Publications (1)

Publication Number Publication Date
JPS57206945A true JPS57206945A (en) 1982-12-18

Family

ID=14007693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56090765A Pending JPS57206945A (en) 1981-06-15 1981-06-15 Mounting base for input/output module and its connecting structure to parallel bus line

Country Status (1)

Country Link
JP (1) JPS57206945A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55124807A (en) * 1979-03-20 1980-09-26 Idec Izumi Corp Control unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55124807A (en) * 1979-03-20 1980-09-26 Idec Izumi Corp Control unit

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