JPS5720449A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To facilitate the operation test of a semiconductor integrated circuit and to improve the yield of the circuit by arranging a nonvolatile floating gate FET at the connecting point or disconnecting point of a plurality of positions on the circuit, selectively altering the memory state of the FET and interrupting or conducting it. CONSTITUTION:An FET in which a floating gate (F.G) and a control gate (C.G) are laminated via an insulating film 22 between n<+> type source and drain regions formed on a p type substrate 21 is used, for example, in an n-channel type MOS circuit. When FETs 112-114 formed in conductive state by injecting holes in the F.G are connected to the disconnecting point between the circuit blocks 110 and 111 as an example, and electrons are injected, for example, in the F.G of the FET 112, and the connecting part is disconnected. FET115 (in which electrons are injected in the F.G) of the interrupted state are connected to the connecting point between the circuit blocks and the wires I-III, and are connected mutually similarly as required. The F.GFET is arranged even at the disconnecting point or the connecting point between the wires. Since the charge injection to the F.G can be readily carried out by the known conventional method, the disconnection or connection of the circuit can be arbitrarily and readily performed.