JPS57203353A - Monitor system for output part of signal channel coder - Google Patents

Monitor system for output part of signal channel coder

Info

Publication number
JPS57203353A
JPS57203353A JP8757381A JP8757381A JPS57203353A JP S57203353 A JPS57203353 A JP S57203353A JP 8757381 A JP8757381 A JP 8757381A JP 8757381 A JP8757381 A JP 8757381A JP S57203353 A JPS57203353 A JP S57203353A
Authority
JP
Japan
Prior art keywords
output
coder
outputs
circuit
fixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8757381A
Other languages
Japanese (ja)
Inventor
Takeo Fukushima
Toshiichi Yamakawa
Takahiro Furukawa
Kyoji Shinohara
Masami Mizuguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8757381A priority Critical patent/JPS57203353A/en
Publication of JPS57203353A publication Critical patent/JPS57203353A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/14—Monitoring arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To detect quickly a falut that affects another coder, by inserting periodically the logic 1 and 0 to a wired OR circuit, extracting these signals again and monitoring the period state of the signal. CONSTITUTION:The frame signal is supplied to a frequency divider 11, and the 0 and 1 level detection pulses are obtained from the divider 11 in the form of the outputs of the AND circuits 12 and 13. Then the output pulse of an inverter 14 is stored in the FF15 and 16 at the detecting points of levels 1 and 0 respectively. Thus a single output is obtained to be turned into a monitor output via an AND circuit 17. If a single channel coder has a fault, the output of the coder is fixed at 0 or 1. When the output is fixed at 0, the outputs of the FF15 and 16 are set at 0 and 1 respectively. While the outputs of the FF15 and 16 are set at 1 and 0 respectively when the output of the coder is fixed at 1. The output of the circuit 17 is set at 0.
JP8757381A 1981-06-09 1981-06-09 Monitor system for output part of signal channel coder Pending JPS57203353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8757381A JPS57203353A (en) 1981-06-09 1981-06-09 Monitor system for output part of signal channel coder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8757381A JPS57203353A (en) 1981-06-09 1981-06-09 Monitor system for output part of signal channel coder

Publications (1)

Publication Number Publication Date
JPS57203353A true JPS57203353A (en) 1982-12-13

Family

ID=13918735

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8757381A Pending JPS57203353A (en) 1981-06-09 1981-06-09 Monitor system for output part of signal channel coder

Country Status (1)

Country Link
JP (1) JPS57203353A (en)

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