JPS5720035A - Synthesizer receiver - Google Patents
Synthesizer receiverInfo
- Publication number
- JPS5720035A JPS5720035A JP9538980A JP9538980A JPS5720035A JP S5720035 A JPS5720035 A JP S5720035A JP 9538980 A JP9538980 A JP 9538980A JP 9538980 A JP9538980 A JP 9538980A JP S5720035 A JPS5720035 A JP S5720035A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- low
- tuning
- high level
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 abstract 1
- 230000007423 decrease Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/34—Muting amplifier when no signal is present or when only weak signals are present, or caused by the presence of noise signals, e.g. squelch systems
- H03G3/348—Muting in response to a mechanical action or to power supply variations, e.g. during tuning; Click removal circuits
Landscapes
- Superheterodyne Receivers (AREA)
- Noise Elimination (AREA)
Abstract
PURPOSE:To eliminate a displeasing tone generated when a reference frequency is set, by operating a squelch circuit for a prescribed time by detecting a tuning pulse after the operation of tuning-speed changeover switch. CONSTITUTION:A tuning-speed changeover switch S is chaged over to differentiate the outputs of inverters 21 and 22 at 23 and 24, whose differential outputs are applied in the form of the sum to the set terminal S of an FF27. Consequently, the terminal Q' of the FF27 is set low. When a tunig pulse is supplied to an input terminal 13, on the other hand, the terminal Q' of an FF25 changes to a low level. Therefore, the output of an OR gate 28 is low during the said period to discharge a capacitor C4, and an output terminal 14 is made high, so that the signal of the terminal 14 decreases the response gain of a low-frequency amplifier to input frequency characteristics. When the terminal Q' of the FF27 returns to the high level, a diode D3 turns off and the terminal 14 is made low a prescribed time later to release the amplifier from the squelch operation. As the terminal Q' of the FF25 change to the high level, the FF27 is reset and the terminal Q' is held at the high level without reference to an input.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9538980A JPS5720035A (en) | 1980-07-11 | 1980-07-11 | Synthesizer receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9538980A JPS5720035A (en) | 1980-07-11 | 1980-07-11 | Synthesizer receiver |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5720035A true JPS5720035A (en) | 1982-02-02 |
JPS6312410B2 JPS6312410B2 (en) | 1988-03-18 |
Family
ID=14136287
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9538980A Granted JPS5720035A (en) | 1980-07-11 | 1980-07-11 | Synthesizer receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5720035A (en) |
-
1980
- 1980-07-11 JP JP9538980A patent/JPS5720035A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6312410B2 (en) | 1988-03-18 |
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