JPS57197992A - Control system for time division multiplex transmission - Google Patents
Control system for time division multiplex transmissionInfo
- Publication number
- JPS57197992A JPS57197992A JP8294581A JP8294581A JPS57197992A JP S57197992 A JPS57197992 A JP S57197992A JP 8294581 A JP8294581 A JP 8294581A JP 8294581 A JP8294581 A JP 8294581A JP S57197992 A JPS57197992 A JP S57197992A
- Authority
- JP
- Japan
- Prior art keywords
- outputs
- sensor switches
- control system
- encoder
- time division
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G08—SIGNALLING
- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
- G08C15/00—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path
- G08C15/06—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path successively, i.e. using time division
- G08C15/12—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path successively, i.e. using time division the signals being represented by pulse characteristics in transmission link
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Selective Calling Equipment (AREA)
Abstract
PURPOSE:To increase the number of controllable loads per one channel, by converting outputs of plural sensor switches, which are connected to a terminal equipment for monitor, to time series signals and encoding and transmitting respective outputs. CONSTITUTION:When one of outputs I1-I8 of sensor switches becomes (1), a D flip flop 9 is set through an OR circuit 7, and an output Q becomes (1). Consequently, a clock oscillator 10 starts the oscillating operation, and outputs Q1-Q8 of a decode counter 11 become (1) successively by clock pulses from the oscillator 10, and outputs I1-I8 of sensor switches are supplied to an encoder 12 through an AND gate 8. State (1) and (0) of respective inputs I1-I8 are encoded (patterned) by the encoder 12 and are transmitted to a main operation panel, which is not shown in figure, through a signal processing circuit 13.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8294581A JPS57197992A (en) | 1981-05-30 | 1981-05-30 | Control system for time division multiplex transmission |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8294581A JPS57197992A (en) | 1981-05-30 | 1981-05-30 | Control system for time division multiplex transmission |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57197992A true JPS57197992A (en) | 1982-12-04 |
JPH0123039B2 JPH0123039B2 (en) | 1989-04-28 |
Family
ID=13788349
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8294581A Granted JPS57197992A (en) | 1981-05-30 | 1981-05-30 | Control system for time division multiplex transmission |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57197992A (en) |
-
1981
- 1981-05-30 JP JP8294581A patent/JPS57197992A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0123039B2 (en) | 1989-04-28 |
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