JPS57192133A - Automatic adjusting device for skew/delay - Google Patents

Automatic adjusting device for skew/delay

Info

Publication number
JPS57192133A
JPS57192133A JP56076982A JP7698281A JPS57192133A JP S57192133 A JPS57192133 A JP S57192133A JP 56076982 A JP56076982 A JP 56076982A JP 7698281 A JP7698281 A JP 7698281A JP S57192133 A JPS57192133 A JP S57192133A
Authority
JP
Japan
Prior art keywords
circuit
delay
output
phase
delay time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56076982A
Other languages
Japanese (ja)
Inventor
Hideyuki Obara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56076982A priority Critical patent/JPS57192133A/en
Publication of JPS57192133A publication Critical patent/JPS57192133A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To automatically obtain a delay time with easy adjustment and high accuracy, by using a voltage controlled delay circuit as a delay element and adjusting a delay time through the assembling of this delay circuit in a PLL circuit. CONSTITUTION:In matching the phase of an output B2 point of a logical circuit 5-1 to be adjusted and an output B1 point of a reference logical circuit 4, switches S1' and S3', S1 and S3 of input and output matrix switch circuits 8 and 7 are operated upwards, respectively. The length of wires from the points B1 and B2 to a phase comparator 9-1 is respectively equal or the shortest. The phase comparator 9-1 compares the phase at the points B1 and B2 and transmits a delay or lead signal to an up/down control circuit 10-1 based on the result of comparison. The circuit 10-1 controls an up/down counter 11-1 based on this signal. This output value controls a voltage control delay circuit 6-1 via a D/A conversion circuit 12-1 to change the delay time of the circuit 6-1.
JP56076982A 1981-05-21 1981-05-21 Automatic adjusting device for skew/delay Pending JPS57192133A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56076982A JPS57192133A (en) 1981-05-21 1981-05-21 Automatic adjusting device for skew/delay

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56076982A JPS57192133A (en) 1981-05-21 1981-05-21 Automatic adjusting device for skew/delay

Publications (1)

Publication Number Publication Date
JPS57192133A true JPS57192133A (en) 1982-11-26

Family

ID=13620978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56076982A Pending JPS57192133A (en) 1981-05-21 1981-05-21 Automatic adjusting device for skew/delay

Country Status (1)

Country Link
JP (1) JPS57192133A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0847139A2 (en) * 1996-12-06 1998-06-10 Nec Corporation Delay difference adjustment circuit and phase adjuster
EP2278790A3 (en) * 2002-02-15 2012-11-21 Avocent Corporation Automatic equalization of video signals

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0847139A2 (en) * 1996-12-06 1998-06-10 Nec Corporation Delay difference adjustment circuit and phase adjuster
EP0847139A3 (en) * 1996-12-06 1998-10-28 Nec Corporation Delay difference adjustment circuit and phase adjuster
EP2278790A3 (en) * 2002-02-15 2012-11-21 Avocent Corporation Automatic equalization of video signals

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