JPS57192052A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57192052A
JPS57192052A JP7741981A JP7741981A JPS57192052A JP S57192052 A JPS57192052 A JP S57192052A JP 7741981 A JP7741981 A JP 7741981A JP 7741981 A JP7741981 A JP 7741981A JP S57192052 A JPS57192052 A JP S57192052A
Authority
JP
Japan
Prior art keywords
substrate
hole
photoresist
etching
thereafter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7741981A
Other languages
Japanese (ja)
Inventor
Osamu Ishihara
Yoshinobu Kadowaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7741981A priority Critical patent/JPS57192052A/en
Publication of JPS57192052A publication Critical patent/JPS57192052A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

PURPOSE:To improve reliability by forming a pedestal for flip chip bonding by machining a semiconductor crystal, facilitating the flattening of the surface, and making it hard to be subjected to thermal expansion. CONSTITUTION:On one surface of a semi-insulating GaAs substrate 8, the part coated by a photoresist 12 and a window 13 are formed. Then, etching is performed, and a trapezoid shaped hole 11 is formed. Thereafter, the photoresist 12 is removed, and metallized layer is formed on the formed surface of the hole 11. Then, the surface of the substrate 8 on which the hole 11 is not formed is ground by etching, mechanical grinding, or combination of both, until the metalized layer 9 is exposed. Thereafter the substrate 8 is bonded to a metal base 7. Finally a surface metal layer 10 is formed.
JP7741981A 1981-05-21 1981-05-21 Semiconductor device Pending JPS57192052A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7741981A JPS57192052A (en) 1981-05-21 1981-05-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7741981A JPS57192052A (en) 1981-05-21 1981-05-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57192052A true JPS57192052A (en) 1982-11-26

Family

ID=13633430

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7741981A Pending JPS57192052A (en) 1981-05-21 1981-05-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57192052A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003019669A1 (en) * 2001-08-31 2003-03-06 Atmel Grenoble S.A. Method for making a colour image sensor with recessed contact apertures prior to thinning
US9018759B2 (en) 2011-10-19 2015-04-28 SK Hynix Inc. Semiconductor package substrate and semiconductor package including the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003019669A1 (en) * 2001-08-31 2003-03-06 Atmel Grenoble S.A. Method for making a colour image sensor with recessed contact apertures prior to thinning
FR2829291A1 (en) * 2001-08-31 2003-03-07 Atmel Grenoble Sa METHOD OF MANUFACTURING COLOR IMAGE SENSOR WITH HOLLOW CONTACT OPENINGS BEFORE THINNING
US6960483B2 (en) 2001-08-31 2005-11-01 Atmel Grenoble S.A. Method for making a color image sensor with recessed contact apertures prior to thinning
CN100356574C (en) * 2001-08-31 2007-12-19 Atmel格勒诺布尔公司 Method for making a colour image sensor with recessed contact apertures prior to thinning
US9018759B2 (en) 2011-10-19 2015-04-28 SK Hynix Inc. Semiconductor package substrate and semiconductor package including the same

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