JPS57191894A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS57191894A
JPS57191894A JP7739981A JP7739981A JPS57191894A JP S57191894 A JPS57191894 A JP S57191894A JP 7739981 A JP7739981 A JP 7739981A JP 7739981 A JP7739981 A JP 7739981A JP S57191894 A JPS57191894 A JP S57191894A
Authority
JP
Japan
Prior art keywords
circuit
terminal
discrimination
output data
setting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7739981A
Other languages
Japanese (ja)
Inventor
Kingo Wakimoto
Koichi Hanamura
Toshio Ichiyama
Hiroshi Miyajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7739981A priority Critical patent/JPS57191894A/en
Publication of JPS57191894A publication Critical patent/JPS57191894A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

PURPOSE:To automate various processings, by providing a controlling circuit, which is operated only for discrimination, to perform the electric discrimination. CONSTITUTION:A controlling circuit 6 having an inverter which is inverted with a >=10V input by setting the ratio of the channel width to the channel length of a depletion load transistor TR to 2 and setting the ratio of an enhancement driver TR to 2 is provided. When a voltage of 5V is applied to a chip enable terminal 5, the circuit 6 is unoperated, and a normal operation is performed. When a >=10V excessive voltage is applied to the terminal 5, the circuit 6 is in the active state, and an address of an ROM7 where discrimination information is stored is selected. Information of the selected address is outputted to an output data terminal 9 through an output data buffer circuit 8 which is in the active state by the terminal 5 to which >=10V excessive voltage is applied.
JP7739981A 1981-05-20 1981-05-20 Semiconductor integrated circuit Pending JPS57191894A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7739981A JPS57191894A (en) 1981-05-20 1981-05-20 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7739981A JPS57191894A (en) 1981-05-20 1981-05-20 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS57191894A true JPS57191894A (en) 1982-11-25

Family

ID=13632811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7739981A Pending JPS57191894A (en) 1981-05-20 1981-05-20 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS57191894A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6427097A (en) * 1987-07-23 1989-01-30 Mitsubishi Electric Corp Mask rom device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6427097A (en) * 1987-07-23 1989-01-30 Mitsubishi Electric Corp Mask rom device

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