JPS57191770A - Transmission system for stop indicating signal - Google Patents

Transmission system for stop indicating signal

Info

Publication number
JPS57191770A
JPS57191770A JP7697181A JP7697181A JPS57191770A JP S57191770 A JPS57191770 A JP S57191770A JP 7697181 A JP7697181 A JP 7697181A JP 7697181 A JP7697181 A JP 7697181A JP S57191770 A JPS57191770 A JP S57191770A
Authority
JP
Japan
Prior art keywords
cpus
stop
indicating signal
signal lines
transmission system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7697181A
Other languages
Japanese (ja)
Inventor
Masaharu Ejiri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7697181A priority Critical patent/JPS57191770A/en
Publication of JPS57191770A publication Critical patent/JPS57191770A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To detect a trap stop signal of a CPU to stop optional plural CPUs. CONSTITUTION:This system consists of n-number of CPUs constituting a multiprocessor system, a common memory CM, a general controller MCC which generalizes and controls all CPUs, and a control panel called a master console MCSL which issues commands to CPUs. Besides normal indicating signal lines 101-10n and response lines 111-11n, CPU conditional stop signal lines 121-12n for signals indicating the stop of respective CPUs and stop indicating signal lines 131-13n from the MCC to CPUs i (i=1-n) are added for respective CPUs.
JP7697181A 1981-05-21 1981-05-21 Transmission system for stop indicating signal Pending JPS57191770A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7697181A JPS57191770A (en) 1981-05-21 1981-05-21 Transmission system for stop indicating signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7697181A JPS57191770A (en) 1981-05-21 1981-05-21 Transmission system for stop indicating signal

Publications (1)

Publication Number Publication Date
JPS57191770A true JPS57191770A (en) 1982-11-25

Family

ID=13620664

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7697181A Pending JPS57191770A (en) 1981-05-21 1981-05-21 Transmission system for stop indicating signal

Country Status (1)

Country Link
JP (1) JPS57191770A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023170800A1 (en) * 2022-03-08 2023-09-14 三菱電機株式会社 Programmable logic controller, cpu unit, control method, and program

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023170800A1 (en) * 2022-03-08 2023-09-14 三菱電機株式会社 Programmable logic controller, cpu unit, control method, and program

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