JPS57190488A - Time base compensating device - Google Patents

Time base compensating device

Info

Publication number
JPS57190488A
JPS57190488A JP56074583A JP7458381A JPS57190488A JP S57190488 A JPS57190488 A JP S57190488A JP 56074583 A JP56074583 A JP 56074583A JP 7458381 A JP7458381 A JP 7458381A JP S57190488 A JPS57190488 A JP S57190488A
Authority
JP
Japan
Prior art keywords
signal
memory
pulse
clock pulse
burst
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56074583A
Other languages
Japanese (ja)
Inventor
Kaichi Tatezawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP56074583A priority Critical patent/JPS57190488A/en
Publication of JPS57190488A publication Critical patent/JPS57190488A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00Details of colour television systems
    • H04N9/79Processing of colour television signals in connection with recording
    • H04N9/87Regeneration of colour television signals
    • H04N9/89Time-base error compensation
    • H04N9/896Time-base error compensation using a digital memory with independent write-in and read-out clock generators

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)

Abstract

PURPOSE:To stabilize an operation against disturbance, etc. without deteriorating its accuracy when correcting at the write side, by shifting in order a period corresponding to a prescribed period of a clock pulse, and executing each compensation in said prescribed period. CONSTITUTION:A composite video signal S1 from an input terminal 1 is converted to a digital signal by an A/D converter 4, and is written in a memory 6. A clock pulse applied to this converter 4, and a clock pulse applied to a memory controlling circuit 7 for controlling the memory 6 are synchronized with a horizontal synchronizing signal of the signal S1 and a burst signal. By a synchronization separating circuit 9 for inputting this signal S1, the horizontal synchronizing signal is separated, the burst signal is extracted by a burst gate 10, frequency of 4 times of a subcarrier is generated from a VCO13, and a pulse of 4 phase is outputted from a 4-phase pulse generating circuit 17. Subsequently, a period corresponding to 4 periods of the pulse is shifted in order, correction is executed at the writing side to the memory 6 in 4 periods, and the operation is stabilized against disturbance, etc. without deteriorating its accuracy.
JP56074583A 1981-05-18 1981-05-18 Time base compensating device Pending JPS57190488A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56074583A JPS57190488A (en) 1981-05-18 1981-05-18 Time base compensating device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56074583A JPS57190488A (en) 1981-05-18 1981-05-18 Time base compensating device

Publications (1)

Publication Number Publication Date
JPS57190488A true JPS57190488A (en) 1982-11-24

Family

ID=13551324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56074583A Pending JPS57190488A (en) 1981-05-18 1981-05-18 Time base compensating device

Country Status (1)

Country Link
JP (1) JPS57190488A (en)

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