JPS57190444A - Communication controlling circuit for high level data link control procedure (hdlc) - Google Patents

Communication controlling circuit for high level data link control procedure (hdlc)

Info

Publication number
JPS57190444A
JPS57190444A JP56074176A JP7417681A JPS57190444A JP S57190444 A JPS57190444 A JP S57190444A JP 56074176 A JP56074176 A JP 56074176A JP 7417681 A JP7417681 A JP 7417681A JP S57190444 A JPS57190444 A JP S57190444A
Authority
JP
Japan
Prior art keywords
hdlc
frame
hdlc circuit
circuit
flag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56074176A
Other languages
Japanese (ja)
Inventor
Isao Nakamura
Takeshi Matoba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kokusai Electric Corp
Original Assignee
Kokusai Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Electric Corp filed Critical Kokusai Electric Corp
Priority to JP56074176A priority Critical patent/JPS57190444A/en
Publication of JPS57190444A publication Critical patent/JPS57190444A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To ease time restrictions on software by switching two circuits with flag detecting functions laternately in every frame to receive data from a communication line. CONSTITUTION:When line data from a receiving line 3 arrives at a line input part 4, a control part 7 makes an HDLC circuit 5 ready for reception. The HDLC circuit 5 detects the starting flag F of a frame 1, receives the data of the frame 1 and start direct memory access (DMA) transfer to a memory in the control part 7. Whe the HDLC circuit 5 starts DMA, the control part 7 makes a HDLC circuit 6 ready for reception. When the end flag of the frame 1, namely the starting flag F' of a frame 2 arrives at the input part, the HDLC circuit 5 stops DMA transfer and the HDLC circuit 6 receives the frame 2 and starts DMA transfer. Hereater, same operation is repeated, so that the HDLC circuits 5, 6 perform signal reception and DMA transfer alternately.
JP56074176A 1981-05-19 1981-05-19 Communication controlling circuit for high level data link control procedure (hdlc) Pending JPS57190444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56074176A JPS57190444A (en) 1981-05-19 1981-05-19 Communication controlling circuit for high level data link control procedure (hdlc)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56074176A JPS57190444A (en) 1981-05-19 1981-05-19 Communication controlling circuit for high level data link control procedure (hdlc)

Publications (1)

Publication Number Publication Date
JPS57190444A true JPS57190444A (en) 1982-11-24

Family

ID=13539586

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56074176A Pending JPS57190444A (en) 1981-05-19 1981-05-19 Communication controlling circuit for high level data link control procedure (hdlc)

Country Status (1)

Country Link
JP (1) JPS57190444A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5161785A (en) * 1974-11-27 1976-05-28 Hitachi Ltd SHINGODENSO HOSHIKI

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5161785A (en) * 1974-11-27 1976-05-28 Hitachi Ltd SHINGODENSO HOSHIKI

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