JPS57189384A - Information processor - Google Patents

Information processor

Info

Publication number
JPS57189384A
JPS57189384A JP56071442A JP7144281A JPS57189384A JP S57189384 A JPS57189384 A JP S57189384A JP 56071442 A JP56071442 A JP 56071442A JP 7144281 A JP7144281 A JP 7144281A JP S57189384 A JPS57189384 A JP S57189384A
Authority
JP
Japan
Prior art keywords
dat
cpu
addresses
memory access
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56071442A
Inventor
Akira Sakauchi
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP56071442A priority Critical patent/JPS57189384A/en
Publication of JPS57189384A publication Critical patent/JPS57189384A/en
Application status is Pending legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Abstract

PURPOSE:To perform control efficiently wherein individual pages admit access from an IOC but not from a CPU by setting DAT not in the CPU but in an MMC. CONSTITUTION:A CPU 22 is not contained with an address conversion machanism DAT and performs memory access by emitting the imaginary addresses formed by programs to a common bus 27, but a main storage control part MMC 21 contains a DAT 23 and performs access of a main storage module by converting the imaginary addresses given from the bus 27 to physical addresses. The control wire in the bus 27 announces whether the request for memory access is given from the CPU 22 or an input-output control unit IOC 24. The DAT 23 consists of a conversion circuit which converts the imaginary addresses to the corresponding physical addresses and an address conversion buffer for increasing the speed of memory access.
JP56071442A 1981-05-14 1981-05-14 Information processor Pending JPS57189384A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56071442A JPS57189384A (en) 1981-05-14 1981-05-14 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56071442A JPS57189384A (en) 1981-05-14 1981-05-14 Information processor

Publications (1)

Publication Number Publication Date
JPS57189384A true JPS57189384A (en) 1982-11-20

Family

ID=13460653

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56071442A Pending JPS57189384A (en) 1981-05-14 1981-05-14 Information processor

Country Status (1)

Country Link
JP (1) JPS57189384A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007129482A1 (en) * 2006-04-06 2007-11-15 Sony Corporation Bridge, processor unit, information processing apparatus and access control method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007129482A1 (en) * 2006-04-06 2007-11-15 Sony Corporation Bridge, processor unit, information processing apparatus and access control method
US8006000B2 (en) 2006-04-06 2011-08-23 Sony Corporation Bridge, processor unit, information processing apparatus, and access control method

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