JPS57189384A - Information processor - Google Patents
Information processorInfo
- Publication number
- JPS57189384A JPS57189384A JP56071442A JP7144281A JPS57189384A JP S57189384 A JPS57189384 A JP S57189384A JP 56071442 A JP56071442 A JP 56071442A JP 7144281 A JP7144281 A JP 7144281A JP S57189384 A JPS57189384 A JP S57189384A
- Authority
- JP
- Japan
- Prior art keywords
- cpu
- dat
- addresses
- memory access
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE:To perform control efficiently wherein individual pages admit access from an IOC but not from a CPU by setting DAT not in the CPU but in an MMC. CONSTITUTION:A CPU 22 is not contained with an address conversion machanism DAT and performs memory access by emitting the imaginary addresses formed by programs to a common bus 27, but a main storage control part MMC 21 contains a DAT 23 and performs access of a main storage module by converting the imaginary addresses given from the bus 27 to physical addresses. The control wire in the bus 27 announces whether the request for memory access is given from the CPU 22 or an input-output control unit IOC 24. The DAT 23 consists of a conversion circuit which converts the imaginary addresses to the corresponding physical addresses and an address conversion buffer for increasing the speed of memory access.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56071442A JPS57189384A (en) | 1981-05-14 | 1981-05-14 | Information processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56071442A JPS57189384A (en) | 1981-05-14 | 1981-05-14 | Information processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57189384A true JPS57189384A (en) | 1982-11-20 |
Family
ID=13460653
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56071442A Pending JPS57189384A (en) | 1981-05-14 | 1981-05-14 | Information processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57189384A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007129482A1 (en) * | 2006-04-06 | 2007-11-15 | Sony Corporation | Bridge, processor unit, information processing apparatus and access control method |
-
1981
- 1981-05-14 JP JP56071442A patent/JPS57189384A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007129482A1 (en) * | 2006-04-06 | 2007-11-15 | Sony Corporation | Bridge, processor unit, information processing apparatus and access control method |
US8006000B2 (en) | 2006-04-06 | 2011-08-23 | Sony Corporation | Bridge, processor unit, information processing apparatus, and access control method |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5764383A (en) | Address converting method and its device | |
ES8103868A1 (en) | Access system for memory modules. | |
JPS57138079A (en) | Information processor | |
JPS57185545A (en) | Information processor | |
JPS5786959A (en) | Data transfer control system | |
JPS5532118A (en) | Data processing system | |
JPS57189384A (en) | Information processor | |
JPS54122059A (en) | Inter-processor information transfer system | |
JPS57117055A (en) | Memory extension system of microcomputer | |
EP0333231A3 (en) | Microcomputer system capable of accessing to memory at high speed | |
JPS56118165A (en) | Processor of video information | |
JPS56157520A (en) | Dma system without cycle steal | |
JPS6426250A (en) | Memory readout circuit for cpu | |
JPS5786180A (en) | Memory device having address converting mechanism | |
JPS5636744A (en) | Microcomputer unit | |
JPS5561866A (en) | Memory designation system | |
JPS56134383A (en) | Data processor | |
JPS54140841A (en) | Memory control system of multiprocessor system | |
FR2639737B1 (en) | INTEGRATED DYNAMIC PROGRAMMING CIRCUIT | |
JPS54122060A (en) | Inter-processor information transfer system | |
JPS6414655A (en) | Data transfer device | |
JPS56137458A (en) | Address conversion system | |
JPS57196338A (en) | Data processor | |
JPS5464435A (en) | Information shunting processing system in channel unit | |
JPS5558873A (en) | Data processor having common memory unit |