JPS57183062A - Patterning layout of tape substrate with inner-lead - Google Patents

Patterning layout of tape substrate with inner-lead

Info

Publication number
JPS57183062A
JPS57183062A JP6882481A JP6882481A JPS57183062A JP S57183062 A JPS57183062 A JP S57183062A JP 6882481 A JP6882481 A JP 6882481A JP 6882481 A JP6882481 A JP 6882481A JP S57183062 A JPS57183062 A JP S57183062A
Authority
JP
Japan
Prior art keywords
inner leads
tape substrate
lead
centerline
patterning layout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6882481A
Other languages
Japanese (ja)
Inventor
Sadazumi Uchiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP6882481A priority Critical patent/JPS57183062A/en
Publication of JPS57183062A publication Critical patent/JPS57183062A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To eliminate the etching difference of inner leads perpendicular to each other and make a patterning layout effective, by providing the inner leads at 45 deg. or 135 deg. inclining to the centerline of a tape substrate. CONSTITUTION:Inner leads 3' and 4' perpendicular to each other are provided at 45 deg. or 135 deg. inclining to the centerline 2 of a tape substrate 1' having an index perforation 6 on both sides. When a plurality of inner leads are formed along the tape substrate, pairs of inner leads are arranged on both sides of the centerline in zigzags. This equlizes the etching of inner leads. A plurality of pairs can be formed on a single substrate.
JP6882481A 1981-05-07 1981-05-07 Patterning layout of tape substrate with inner-lead Pending JPS57183062A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6882481A JPS57183062A (en) 1981-05-07 1981-05-07 Patterning layout of tape substrate with inner-lead

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6882481A JPS57183062A (en) 1981-05-07 1981-05-07 Patterning layout of tape substrate with inner-lead

Publications (1)

Publication Number Publication Date
JPS57183062A true JPS57183062A (en) 1982-11-11

Family

ID=13384839

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6882481A Pending JPS57183062A (en) 1981-05-07 1981-05-07 Patterning layout of tape substrate with inner-lead

Country Status (1)

Country Link
JP (1) JPS57183062A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4942859B1 (en) * 1964-01-27 1974-11-18
JPS5461468A (en) * 1977-10-26 1979-05-17 Hitachi Ltd Film wiring substrate and electronic components using it

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4942859B1 (en) * 1964-01-27 1974-11-18
JPS5461468A (en) * 1977-10-26 1979-05-17 Hitachi Ltd Film wiring substrate and electronic components using it

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