JPS57182854A - Check method for self-diagnostic output - Google Patents

Check method for self-diagnostic output

Info

Publication number
JPS57182854A
JPS57182854A JP6811381A JP6811381A JPS57182854A JP S57182854 A JPS57182854 A JP S57182854A JP 6811381 A JP6811381 A JP 6811381A JP 6811381 A JP6811381 A JP 6811381A JP S57182854 A JPS57182854 A JP S57182854A
Authority
JP
Japan
Prior art keywords
bit
output
bit patterns
supplied
output port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6811381A
Other languages
Japanese (ja)
Inventor
Shingo Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP6811381A priority Critical patent/JPS57182854A/en
Publication of JPS57182854A publication Critical patent/JPS57182854A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits

Abstract

PURPOSE:To make check possible with the OR output of a bit pattern supplied to a peripheral circuit, by outputting the bit pattern, by which normality or abnormality of respective lines are discriminated individually, in time division from an output port. CONSTITUTION:Data is transmitted from a bus line 1 to an output port 2 connected to the bus line 1, and n-bit bit patterns are properly outputted from plural output lines 31-3n (n is an optional integer) connected to the output port 2. Peripheral circuits (additional circuits) of the device are controlled in accordance with these bit patterns. An OR circuit 6 which operates the OR of bit patterns supplied to output lines 31-3n is provided for the purpose of diagnosing whether bit patterns supplied actually to peripheral circuits are proper or not, thereby simplifying the feedback system such as diagnostic line 7 and a diagnostic input port 8.
JP6811381A 1981-05-08 1981-05-08 Check method for self-diagnostic output Pending JPS57182854A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6811381A JPS57182854A (en) 1981-05-08 1981-05-08 Check method for self-diagnostic output

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6811381A JPS57182854A (en) 1981-05-08 1981-05-08 Check method for self-diagnostic output

Publications (1)

Publication Number Publication Date
JPS57182854A true JPS57182854A (en) 1982-11-10

Family

ID=13364357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6811381A Pending JPS57182854A (en) 1981-05-08 1981-05-08 Check method for self-diagnostic output

Country Status (1)

Country Link
JP (1) JPS57182854A (en)

Similar Documents

Publication Publication Date Title
GB2195185B (en) Testing circuits comprising integrated circuits provided on a carrier
ES8102809A1 (en) Sterilizing apparatus and integrated sterilizer control
GR860073B (en) Improvements in and relating to integrated circuits
GB1390140A (en) Interconnection tester system
GB1534482A (en) Data processor including a status reporting and analysing system
YU45696B (en) COMMUNICATION MULTIPLEXER DEVICE WITH VARIABLE PRIORITY PROGRAM
GB2121997A (en) Testing modular data processing systems
JPS57182854A (en) Check method for self-diagnostic output
US4697234A (en) Data processing module with serial test data paths
US5511225A (en) Programmable controller for controlling output of control system by having configuration circuit cooperating with monitor logic to selectively transmit return output frame
JPS5231629A (en) Data communiction system
JPS5444480A (en) Package for integrated circuit
GB1402080A (en) Error checking apparatus for group of control logic units
KR840000385B1 (en) Bus connection system
SU966904A1 (en) Pulse distributor
JPS56124956A (en) Double information processing equipment
JPS6426175A (en) Test data preparing system for logic integrated circuit
JPS57206961A (en) Logical integrated circuit
JPS56145426A (en) Serial data transferring method
JPS6417460A (en) Semiconductor logic integrated circuit device
SU706849A1 (en) Device for monitoring digital units
JPH0694804A (en) Ic testing device
JPS5619253A (en) Fault detecting system
JPS5671125A (en) Data processing device
JPS5627427A (en) Diagnostic system of selector channel