JPS57174705A - Programmable logic controller - Google Patents

Programmable logic controller

Info

Publication number
JPS57174705A
JPS57174705A JP5960081A JP5960081A JPS57174705A JP S57174705 A JPS57174705 A JP S57174705A JP 5960081 A JP5960081 A JP 5960081A JP 5960081 A JP5960081 A JP 5960081A JP S57174705 A JPS57174705 A JP S57174705A
Authority
JP
Japan
Prior art keywords
input
output
forcible operation
data
rewriting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5960081A
Other languages
Japanese (ja)
Inventor
Yukio Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Tateisi Electronics Co
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tateisi Electronics Co, Omron Tateisi Electronics Co filed Critical Tateisi Electronics Co
Priority to JP5960081A priority Critical patent/JPS57174705A/en
Publication of JPS57174705A publication Critical patent/JPS57174705A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/058—Safety, monitoring
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/11—Plc I-O input output
    • G05B2219/1162—Forcing I-O
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/13—Plc programming
    • G05B2219/13016—Jump while output is disabled, or disabling output when running test instruction

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE:To eliminate the logical conflict of a program in the output simulation mode with a simple constitution, by rewriting the designated output data of an input/output memory with a forcible operation input and then inhibiting the rewriting as an output data for execution of an instructuion. CONSTITUTION:A program console 8 supplies with a forcible operation an input/ output address for forcible operation and the set or reset data to the input/output address. Receiving the forcible operation input, an access is given to an input/output memory 7 after the working cycle of a control circuit 6C functioning as an input/output replacing means and before the working cycle of an arithmetic control circuit 5 functioning as an instruction executing means. Then the supplied set or reset data is forcibly written into the supplied input/output address. The data rewriting is inhibited 17 concerning the input/output address which is forcibly supplied at the memory 7 when the circuit 5 is working in a certain period of the forcible operation input. As a result, the input/output simulation is facilitated to eliminate the logical conflict of a program in the output simulation mode.
JP5960081A 1981-04-20 1981-04-20 Programmable logic controller Pending JPS57174705A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5960081A JPS57174705A (en) 1981-04-20 1981-04-20 Programmable logic controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5960081A JPS57174705A (en) 1981-04-20 1981-04-20 Programmable logic controller

Publications (1)

Publication Number Publication Date
JPS57174705A true JPS57174705A (en) 1982-10-27

Family

ID=13117898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5960081A Pending JPS57174705A (en) 1981-04-20 1981-04-20 Programmable logic controller

Country Status (1)

Country Link
JP (1) JPS57174705A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6286407A (en) * 1985-10-11 1987-04-20 Omron Tateisi Electronics Co Programmable controller

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53117182A (en) * 1977-03-23 1978-10-13 Sharp Corp Sequence controller

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53117182A (en) * 1977-03-23 1978-10-13 Sharp Corp Sequence controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6286407A (en) * 1985-10-11 1987-04-20 Omron Tateisi Electronics Co Programmable controller

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