JPS57173280A - Signal suppression circuit - Google Patents

Signal suppression circuit

Info

Publication number
JPS57173280A
JPS57173280A JP56058276A JP5827681A JPS57173280A JP S57173280 A JPS57173280 A JP S57173280A JP 56058276 A JP56058276 A JP 56058276A JP 5827681 A JP5827681 A JP 5827681A JP S57173280 A JPS57173280 A JP S57173280A
Authority
JP
Japan
Prior art keywords
blanking period
current
trs
suppression circuit
signal suppression
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56058276A
Other languages
Japanese (ja)
Inventor
Masami Onishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56058276A priority Critical patent/JPS57173280A/en
Publication of JPS57173280A publication Critical patent/JPS57173280A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Picture Signal Circuits (AREA)

Abstract

PURPOSE:To simplify and make constitution suitable for a monolithic integrated circuit by compensating an offset voltage and variation of suppression characteristics due to this voltage while exercising control in a blanking period. CONSTITUTION:When the collector potential of a transistor (TR) 11 is lower than that of a TR12 in a blanking period, the base potential of a TR25 is higher than that of a TR26. On the other hand, a synchronizing pulse from a synchronizing pulse signal source 36 synchronizing with the blanking period turns on a TR39 and a current from a current source 37 flows through a TR40. Therefore, a similar current flows through a TR41. Then, TRs 25 and 26 constitute a differential amplifier and their difference current is charged in a capacitor 42, and consequently the collector potential of the TR12 drops. In some period other than the blanking period, TRs 25 and 26 are cut off, thus realizing the operation of a signal suppression circuit.
JP56058276A 1981-04-16 1981-04-16 Signal suppression circuit Pending JPS57173280A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56058276A JPS57173280A (en) 1981-04-16 1981-04-16 Signal suppression circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56058276A JPS57173280A (en) 1981-04-16 1981-04-16 Signal suppression circuit

Publications (1)

Publication Number Publication Date
JPS57173280A true JPS57173280A (en) 1982-10-25

Family

ID=13079657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56058276A Pending JPS57173280A (en) 1981-04-16 1981-04-16 Signal suppression circuit

Country Status (1)

Country Link
JP (1) JPS57173280A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60186754U (en) * 1984-05-21 1985-12-11 ソニー株式会社 Video sync signal expander

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60186754U (en) * 1984-05-21 1985-12-11 ソニー株式会社 Video sync signal expander
JPH0419883Y2 (en) * 1984-05-21 1992-05-07

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