JPS5717051A - Dma address generating method - Google Patents
Dma address generating methodInfo
- Publication number
- JPS5717051A JPS5717051A JP9200080A JP9200080A JPS5717051A JP S5717051 A JPS5717051 A JP S5717051A JP 9200080 A JP9200080 A JP 9200080A JP 9200080 A JP9200080 A JP 9200080A JP S5717051 A JPS5717051 A JP S5717051A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- data
- register
- transfers
- bits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
PURPOSE:To simplify a process of picture, a storage and the like, by generating the discontinuous direct memory access address and supplying directly the data corresponding to a memory region. CONSTITUTION:The field transfer clock phip supplies the data of a field to the vertical shift register of an image sensor register 10 with a clock. A horizontal shift clock phiH transfers the data of a bit with a clock and then transfers 8 bits en bloc onto the data bus in the form of a byte during the direct memory access DMA. Furthermore, a vertical shift clock phiV is used to shift the vertical register of a register for a CCD image sensor and resets a lower binary counter 16 every time a new line is delivered to increase an upper binary counter. Accordingly, the address of 32 bits is generated at intervals, and the data of 2 fields and 1 frame can be transferred to the memory area.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9200080A JPS5717051A (en) | 1980-07-05 | 1980-07-05 | Dma address generating method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9200080A JPS5717051A (en) | 1980-07-05 | 1980-07-05 | Dma address generating method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5717051A true JPS5717051A (en) | 1982-01-28 |
Family
ID=14042142
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9200080A Pending JPS5717051A (en) | 1980-07-05 | 1980-07-05 | Dma address generating method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5717051A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03219043A (en) * | 1990-01-23 | 1991-09-26 | Topy Ind Ltd | Low carbon boron steel track shoe and its manufacture |
JP2009229353A (en) * | 2008-03-25 | 2009-10-08 | Seiko Epson Corp | Device and system for sensing gas |
-
1980
- 1980-07-05 JP JP9200080A patent/JPS5717051A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03219043A (en) * | 1990-01-23 | 1991-09-26 | Topy Ind Ltd | Low carbon boron steel track shoe and its manufacture |
JP2009229353A (en) * | 2008-03-25 | 2009-10-08 | Seiko Epson Corp | Device and system for sensing gas |
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