JPS57168552A - Data transfer system - Google Patents
Data transfer systemInfo
- Publication number
- JPS57168552A JPS57168552A JP5349681A JP5349681A JPS57168552A JP S57168552 A JPS57168552 A JP S57168552A JP 5349681 A JP5349681 A JP 5349681A JP 5349681 A JP5349681 A JP 5349681A JP S57168552 A JPS57168552 A JP S57168552A
- Authority
- JP
- Japan
- Prior art keywords
- transmitter
- slot
- receiving side
- transmitting side
- state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/42—Loop networks
- H04L12/427—Loop networks with decentralised control
- H04L12/43—Loop networks with decentralised control with synchronous transmission, e.g. time division multiplex [TDM], slotted rings
Abstract
PURPOSE:To ensure an assured synchronizing operation through a transmitter of the transmitting side, by providing a field at a part of a slot in order to transmit the state of a transmitter of the receiving side to the transmitter of the transmitting side. CONSTITUTION:Transmitters 1a-1c are connected via a transmission line 2, and terminals are connected to these transmitters respectively. A controller 4 monitors and controls the line 2. When the sending-back of an affirmative answer 32 is over at the receiving side of the transmitter, a status bit 61 is set in a busy state. Then the information showing the ready stare is put on the bit 61 to be transmitted. A data transfer slot 33 arriving later is received assuredly and processed. On the other hand, the transmitter of the transmitting side prepares for reception of the data when it receives a slot 32 showing an affirmative answer. After the preparation is over, the conditional data is transmitted. Then the actual transmission is started after the transmitter of the receiving side detects the ready state.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5349681A JPS57168552A (en) | 1981-04-09 | 1981-04-09 | Data transfer system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5349681A JPS57168552A (en) | 1981-04-09 | 1981-04-09 | Data transfer system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57168552A true JPS57168552A (en) | 1982-10-16 |
Family
ID=12944435
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5349681A Pending JPS57168552A (en) | 1981-04-09 | 1981-04-09 | Data transfer system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57168552A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6243237A (en) * | 1985-08-20 | 1987-02-25 | Hitachi Ltd | Transmission system for looped network |
-
1981
- 1981-04-09 JP JP5349681A patent/JPS57168552A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6243237A (en) * | 1985-08-20 | 1987-02-25 | Hitachi Ltd | Transmission system for looped network |
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