JPS57167199A - Associative memory device - Google Patents

Associative memory device

Info

Publication number
JPS57167199A
JPS57167199A JP56051371A JP5137181A JPS57167199A JP S57167199 A JPS57167199 A JP S57167199A JP 56051371 A JP56051371 A JP 56051371A JP 5137181 A JP5137181 A JP 5137181A JP S57167199 A JPS57167199 A JP S57167199A
Authority
JP
Japan
Prior art keywords
cycle
data
word
readout
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56051371A
Other languages
Japanese (ja)
Inventor
Tadanobu Nikaido
Takeshi Ogura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56051371A priority Critical patent/JPS57167199A/en
Publication of JPS57167199A publication Critical patent/JPS57167199A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To decrease the number of readout terminals and to increase the readout speed, by outputting the storage data of the word to be delivered after excluding the whole or a part of the subject to be retrieved among the above- mentioned storage data.
CONSTITUTION: When the retrieving is instructed in the 1st cycle, a cell array 1 compares the storage data of each word and the contents of a retrieving data register 3 to discriminate the coincident word. When the 1st and 2nd separation designating signals 7 and 14 are supplied in the 2nd cycle, the 1st and 2nd separating circuits 6 and 13 perform the separation. When the readout is instructed in the 3rd cycle, the storage data of the word coincident with the register 3 is read out of the array 1. Then an output is instructed in the 4th cycle, and as a result the readout data of the array 1 is stored in on output data register 10 and the output of the circuit 13 is stored in a field signal register 16 and they are selected by an output data selector 11, then outputted.
COPYRIGHT: (C)1982,JPO&Japio
JP56051371A 1981-04-06 1981-04-06 Associative memory device Pending JPS57167199A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56051371A JPS57167199A (en) 1981-04-06 1981-04-06 Associative memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56051371A JPS57167199A (en) 1981-04-06 1981-04-06 Associative memory device

Publications (1)

Publication Number Publication Date
JPS57167199A true JPS57167199A (en) 1982-10-14

Family

ID=12885079

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56051371A Pending JPS57167199A (en) 1981-04-06 1981-04-06 Associative memory device

Country Status (1)

Country Link
JP (1) JPS57167199A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63298893A (en) * 1987-05-29 1988-12-06 Nippon Telegr & Teleph Corp <Ntt> Associative memory device
JPH05159584A (en) * 1991-12-06 1993-06-25 Mitsubishi Electric Corp Associative memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63298893A (en) * 1987-05-29 1988-12-06 Nippon Telegr & Teleph Corp <Ntt> Associative memory device
JPH05159584A (en) * 1991-12-06 1993-06-25 Mitsubishi Electric Corp Associative memory

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