JPS57166063A - Semiconductor ic - Google Patents

Semiconductor ic

Info

Publication number
JPS57166063A
JPS57166063A JP56050737A JP5073781A JPS57166063A JP S57166063 A JPS57166063 A JP S57166063A JP 56050737 A JP56050737 A JP 56050737A JP 5073781 A JP5073781 A JP 5073781A JP S57166063 A JPS57166063 A JP S57166063A
Authority
JP
Japan
Prior art keywords
gate
amplifier
source
drain
devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56050737A
Other languages
Japanese (ja)
Inventor
Tatsuo Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56050737A priority Critical patent/JPS57166063A/en
Publication of JPS57166063A publication Critical patent/JPS57166063A/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE: To realize a high speed amplifier with a higher driving capability by a method wherein an amplifier is controlled by clock signals and is provided with a boost trap in a buffer amplifier transmitting to the next stage the signals supplied by the preceding stage.
CONSTITUTION: A buffer amplifier 2 consists of enhancement type FET devices 16 and 17 and depletion type FET device 11 and 12, with an input terminal 1 connected to the device 16 source and the device 16 drain is connected to the device 11 gate. The device 11 drain is connected to the device 12 source and the device 12 gate is connected to a clock input terminal 13. The device 16 gate is connected to the device 17 gate and the device 17 source is connected to a power source terminal 9. The device 17 drain is connected to the node between the devices 16 and 17 and is connected to the node between the devices 11 and 12 through a capacitor 15. This realizes a quick charging of the capacitor 15 which provides the amplifier 2 with a high speed feature.
COPYRIGHT: (C)1982,JPO&Japio
JP56050737A 1981-04-03 1981-04-03 Semiconductor ic Pending JPS57166063A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56050737A JPS57166063A (en) 1981-04-03 1981-04-03 Semiconductor ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56050737A JPS57166063A (en) 1981-04-03 1981-04-03 Semiconductor ic

Publications (1)

Publication Number Publication Date
JPS57166063A true JPS57166063A (en) 1982-10-13

Family

ID=12867149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56050737A Pending JPS57166063A (en) 1981-04-03 1981-04-03 Semiconductor ic

Country Status (1)

Country Link
JP (1) JPS57166063A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01216607A (en) * 1988-02-24 1989-08-30 Nec Corp Amplifier circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01216607A (en) * 1988-02-24 1989-08-30 Nec Corp Amplifier circuit

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