JPH01216607A - Amplifier circuit - Google Patents

Amplifier circuit

Info

Publication number
JPH01216607A
JPH01216607A JP63042742A JP4274288A JPH01216607A JP H01216607 A JPH01216607 A JP H01216607A JP 63042742 A JP63042742 A JP 63042742A JP 4274288 A JP4274288 A JP 4274288A JP H01216607 A JPH01216607 A JP H01216607A
Authority
JP
Japan
Prior art keywords
transistor
drain
current
terminal
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63042742A
Other languages
Japanese (ja)
Other versions
JPH0695614B2 (en
Inventor
Toshiyuki Eto
江藤 俊之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63042742A priority Critical patent/JPH0695614B2/en
Publication of JPH01216607A publication Critical patent/JPH01216607A/en
Publication of JPH0695614B2 publication Critical patent/JPH0695614B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE:To prevent the generation of waveform distortion and to reduce the power consumption by adopting the constitution such that a 1st transistor(TR) whose drain is connected to an input terminal of a current mirror circuit and a 2nd TR whose source is connected to the output terminal of the current mirror circuit. CONSTITUTION:An output current is supplied from a TR Q2 in a positive half cycle of an input signal V1, a drain current of the TR Q2 in this case is the sum of an output current and a drain current of a TR Q4 and a TR Q1 is driven in the OFF state by the input signal V1. Thus, the drain current of the TR Q4 is decreased and the drain current of the TR Q2 is nearly equal to the output current. Moreover, in a negative half cycle of the input signal V1, the output current is supplied from the TR Q4, and as the amplitude of the input signal V1 increases, the drain current of the TR Q1 is increased. Thus, the drain current of the TR Q4 is increased, then the increase in the output current is sufficiently supplied to prevent the generation of wavelength distortion.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は増幅回路に関し、特に集積回路の電圧バッファ
回路等に適した増幅回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an amplifier circuit, and particularly to an amplifier circuit suitable for a voltage buffer circuit of an integrated circuit.

〔従来の技術〕[Conventional technology]

従来、この種の増幅回路は種々提案されているが、その
中の一つに、第3図に示すようなソース・フォロアー回
路として知られている回路がある。
Various amplifier circuits of this type have been proposed in the past, and one of them is a circuit known as a source follower circuit as shown in FIG.

この回路は、トランジスタQ1と定電流源回路IG2と
で構成され、トランジスタQlのソースは定電流源回路
IG2を介して接地端子に接続されるとともに1信号出
力端子ToK接続され、ドレインは電源雷、圧Vcc端
子に接続され、ゲートは信号入力端子TIK接続されて
いる。
This circuit is composed of a transistor Q1 and a constant current source circuit IG2, the source of the transistor Q1 is connected to the ground terminal via the constant current source circuit IG2, and is also connected to the 1 signal output terminal ToK, and the drain is connected to a power supply lightning, The gate is connected to the voltage Vcc terminal, and the gate is connected to the signal input terminal TIK.

信号入力端子Tlに印加された入力信号Vlは、負荷抵
抗に依存せず、はぼ電圧利得1で信号出力端子TOに出
力信号Voとして現われ、従って、負荷側を低インピー
ダンスとするととKより電力利得を得ることができる。
The input signal Vl applied to the signal input terminal Tl does not depend on the load resistance and appears as the output signal Vo at the signal output terminal TO with a voltage gain of 1. Therefore, if the load side is set to a low impedance, the power is lower than K. gain can be obtained.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の増幅回路は、負荷側への吐き出し電流の
供給能力はほぼ無制限であるが吸い込み電流の供給能力
は定電流源回路IG2の電流値で規制される。
In the conventional amplifier circuit described above, the ability to supply a source current to the load side is almost unlimited, but the ability to supply a sink current is regulated by the current value of the constant current source circuit IG2.

従って、負荷抵抗が低く出力信号Voの振幅が大きいと
きは波形歪みを生じ、この波形歪みを抑える為には、定
電流源回路Io2の電流値を大きく設定しておく必要が
ある。これは必然的に消費電力の増加を招き、許容消費
電力の小さい集積回路には適用できないという欠点があ
った。
Therefore, when the load resistance is low and the amplitude of the output signal Vo is large, waveform distortion occurs, and in order to suppress this waveform distortion, it is necessary to set the current value of the constant current source circuit Io2 large. This inevitably leads to an increase in power consumption, and has the disadvantage that it cannot be applied to integrated circuits with small allowable power consumption.

本発明の目的は、波形歪みを抑えかつ消費電力を低減す
ることができ、適用範囲を拡大するととができる増幅回
路を提供することKある。
An object of the present invention is to provide an amplifier circuit that can suppress waveform distortion, reduce power consumption, and expand the range of application.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の増幅回路は、ゲートを信号入力端子と接続しソ
ースを第1の電源電圧端子と接続した一導電型の第1の
トランジスタと、ゲートを前記信号入力端子と接続しド
レインを前記第1の電源電圧端子と接続しソースを信号
出力端子と接続した逆導電型の第2のトランジスタと、
逆導電型の第3及び第4のトランジスタを備えこの第3
のトランジスタのドレインを入力端として前記第1のト
ランジスタのドレインと接続し前記第4のトランジスタ
のドレインを出力端として前記信号出力端子と接続しこ
れら第3及び第4のトランジスタのソースを第2の電源
電圧端子と接続するカレントミラー回路とを有している
The amplifier circuit of the present invention includes a first transistor of one conductivity type having a gate connected to a signal input terminal and a source connected to a first power supply voltage terminal; a gate connected to the signal input terminal and a drain connected to the first transistor; a second transistor of opposite conductivity type connected to the power supply voltage terminal of the transistor and having its source connected to the signal output terminal;
The third transistor includes third and fourth transistors of opposite conductivity types.
The drain of the transistor is connected as an input terminal to the drain of the first transistor, the drain of the fourth transistor is connected as an output terminal to the signal output terminal, and the sources of the third and fourth transistors are connected as an input terminal to the drain of the first transistor. It has a current mirror circuit connected to a power supply voltage terminal.

また、ゲートを信号入力端子と接続しドレインを前記第
1の電源電圧端子と接続した逆導電型の第5のトランジ
スタと、一端をこの第5のトランジスタのソースと接続
し他端を前記第2の電源電圧端子と接続した定電流源回
路とを設け、前記第1のトランジスタのゲートを前記第
5のトランジスタのソースと接続した構成を有している
Further, a fifth transistor of a reverse conductivity type having a gate connected to the signal input terminal and a drain connected to the first power supply voltage terminal; one end connected to the source of the fifth transistor and the other end connected to the second transistor; A constant current source circuit connected to the power supply voltage terminal of is provided, and the gate of the first transistor is connected to the source of the fifth transistor.

〔実施例〕〔Example〕

次に1本発明の実施例について図面を参照して説明する
Next, an embodiment of the present invention will be described with reference to the drawings.

第1図は本発明の第1の実施例を示す回路図でちる。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

この実施例は、ゲートを信号入力端子TIと接続しソー
スを電源電圧Vcc端子と接続した一導電型の第1のト
ランジスタQ1と、ゲートを信号入力端子Tlと接続し
ソースを電源電圧Vcc端子と接続しドレインを信号出
力端子Toと接続した逆導電型の第2のトランジスタQ
2と、通導[型の第3及び第4のトランジスタQ3.Q
4を備え、トランジスタQ3のドレインを入力端として
トランジスタQlのドレインと接続し、トランジスタQ
4のドレインを出力端として信号出力端子TOと接続し
、トランジスタQs 、 Q4のソースを共に接地端子
と接続したカレントミラー回路1とを有する構成となっ
ている。
This embodiment includes a first transistor Q1 of one conductivity type whose gate is connected to a signal input terminal TI and whose source is connected to a power supply voltage Vcc terminal, and whose gate is connected to a signal input terminal Tl and whose source is connected to a power supply voltage Vcc terminal. a second transistor Q of opposite conductivity type connected and having its drain connected to the signal output terminal To;
2, and third and fourth transistors Q3 . Q
4, the drain of the transistor Q3 is connected to the drain of the transistor Ql as an input terminal, and the drain of the transistor Q3 is connected to the drain of the transistor Ql.
The current mirror circuit 1 has a drain connected to a signal output terminal TO as an output terminal, and a current mirror circuit 1 in which the sources of transistors Qs and Q4 are both connected to a ground terminal.

この実施例では、入力信号Vtの正の半サイクルでは、
出力電流はトランジスタQ2から供給されるが、このと
き、トランジスタQ!のドレイン電流は出力電流とトラ
ンジスタQ4のドレイン電流であり、入力信号vlVc
よりトランジスタQ1がオフ方向に追い込まれるので、
トランジスタQ4のドレイン電流は小さくなり、従って
トランジスタQ2のドレイン電流はほぼ出力電流に等し
くなる。
In this example, in the positive half cycle of the input signal Vt,
The output current is supplied from transistor Q2, but at this time, transistor Q! The drain current of is the output current and the drain current of transistor Q4, and the input signal vlVc
Since transistor Q1 is forced into the off direction,
The drain current of transistor Q4 becomes small, so that the drain current of transistor Q2 becomes approximately equal to the output current.

また、入力信号Vlの負の半サイクルでは、出力電流は
トランジスタQ4から供給されるが、このとき、入力信
号vlの振幅が大きくなるにつれトランジスタQ1のド
レイン電流も増加し、従ってトランジスタQ4のドレイ
ン電流も増加して出力電流の増加に対し不足なく供給す
ることができ、波形歪みが発生することを防止する。こ
のことから無信号時のトランジスタQ4のドレイン電流
は、入力信号vlの大振幅時に比べ小さく抑えることが
できる。
Also, in the negative half cycle of the input signal Vl, the output current is supplied from the transistor Q4, but at this time, as the amplitude of the input signal vl increases, the drain current of the transistor Q1 also increases, and therefore the drain current of the transistor Q4 increases. This also increases the output current so that it can be supplied without shortage to meet the increase in output current, thereby preventing waveform distortion from occurring. Therefore, the drain current of the transistor Q4 when there is no signal can be suppressed to be smaller than when the input signal vl has a large amplitude.

さらにトランジスタQ4のドレイン電流は、所謂負帰還
による制御で祉ないので不安定現象は生じない。
Furthermore, since the drain current of the transistor Q4 is controlled by so-called negative feedback, no instability occurs.

第2図は本発明の第2の実施例を示す回路図である。FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

この実施例が第1の実施例と相違する点は、ゲートを信
号入力端子TIと接続しドレインを電源電圧Vcc端子
と接続した逆導電圧の第5のトランジスタQ5と、一端
をこのトランジスタQsのソースと接続し仙痛を接地端
子と接続した定電流源回路Io1とから構成されたソー
ス・フォロアー回路を設け、第1のトランジスタQlの
ゲートをトランジスタQ6のソースと接続した構成とし
、第1の実施例:C対し、無信号時のトランジスタQh
Q−のスレッシ3ルド電圧による消費電流のばらつきを
小さくした点にある。
The difference between this embodiment and the first embodiment is that a fifth transistor Q5 of opposite conduction voltage has its gate connected to the signal input terminal TI and its drain connected to the power supply voltage Vcc terminal, and one end of this transistor Qs. A source follower circuit consisting of a constant current source circuit Io1 connected to the source and the colic connected to the ground terminal is provided, the gate of the first transistor Ql is connected to the source of the transistor Q6, and the first Example: For C, transistor Qh when there is no signal
The point is that the variation in current consumption due to the threshold voltage of Q- is reduced.

即ち、トランジスタQ4のドレイン電流はトランジスタ
Q1のドレイン電流に依存するが、トランジスタQ□の
ゲート・ソース電圧はほぼ出力端子Toの直流電位と電
源電圧Vccにより定まり、トランジスタQs、Qtの
ゲート・ソース電圧には依存しない。
That is, the drain current of the transistor Q4 depends on the drain current of the transistor Q1, but the gate-source voltage of the transistor Q□ is determined approximately by the DC potential of the output terminal To and the power supply voltage Vcc, and the gate-source voltage of the transistors Qs and Qt. does not depend on

従って、トランジスタQs、Q鵞のスレッシlルビ電圧
のばらつきに対し不感となる。
Therefore, it is insensitive to variations in the threshold voltages of the transistors Qs and Q1.

〔発明の効果〕〔Effect of the invention〕

以上説明したように1本発明は第3及び第4のトランジ
スタを備えたカレントミラー回路と、ドレインをこのカ
レントミラー回路の入力端と接続する第1のトランジス
タと、ソースをこのカレントミラー回路の出力端と接続
する第2のトランジスタとを備えた構成とすることKよ
り、波形歪みの発生を防止しかつ消費電力を低減するこ
とができ、集積回路への適用範囲を拡大することができ
る効果がある。
As explained above, the present invention includes a current mirror circuit including third and fourth transistors, a first transistor whose drain is connected to the input terminal of this current mirror circuit, and whose source is connected to the output terminal of this current mirror circuit. By adopting a configuration including a second transistor connected to the end, it is possible to prevent waveform distortion, reduce power consumption, and expand the range of application to integrated circuits. be.

また、第5のトランジスタと定電流源回路とで構成され
たソース・フォロアー回路を介して第1のトランジスタ
のゲートと信号入力端子とを接続する構成とするととK
より、トランジスタのスレッシ冒ルド電圧のばらつきK
よる消費電流のばらつきを除去することができる効果が
ある。
Further, if the gate of the first transistor and the signal input terminal are connected via a source follower circuit composed of a fifth transistor and a constant current source circuit, then K
Therefore, the variation in the threshold voltage of the transistor K
This has the effect of eliminating variations in current consumption due to

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例を示す回路図、第2図社
本発明の第2の実施例を示す回路図、第3図は従来の増
幅回路の一例を示す回路図である。 1・・・・・・カレントミラー回路、Iol、 Ioz
・・・・・・定電流源回路b Qt〜Qs・・・・・・
トランジスタ。 代理人 弁理士  内 原   晋
Fig. 1 is a circuit diagram showing a first embodiment of the present invention, Fig. 2 is a circuit diagram showing a second embodiment of the present invention, and Fig. 3 is a circuit diagram showing an example of a conventional amplifier circuit. . 1...Current mirror circuit, Iol, Ioz
... Constant current source circuit b Qt~Qs...
transistor. Agent Patent Attorney Susumu Uchihara

Claims (2)

【特許請求の範囲】[Claims] (1)ゲートを信号入力端子と接続しソースを第1の電
源電圧端子と接続した一導電型の第1のトランジスタと
、ゲートを前記信号入力端子と接続しドレインを前記第
1の電源電圧端子と接続しソースを信号出力端子と接続
した逆導電型の第2のトランジスタと、逆導電型の第3
及び第4のトランジスタを備えこの第3のトランジスタ
のドレインを入力端として前記第1のトランジスタのド
レインと接続し前記第4のトランジスタのドレインを出
力端として前記信号出力端子と接続しこれら第3及び第
4のトランジスタのソースを第2の電源電圧端子と接続
するカレントミラー回路とを有することを特徴とする増
幅回路。
(1) a first transistor of one conductivity type having a gate connected to a signal input terminal and a source connected to a first power supply voltage terminal; a gate connected to the signal input terminal and a drain connected to the first power supply voltage terminal; a second transistor of the opposite conductivity type, whose source is connected to the signal output terminal;
and a fourth transistor, the drain of the third transistor is connected as an input terminal to the drain of the first transistor, and the drain of the fourth transistor is connected as an output terminal to the signal output terminal. An amplifier circuit comprising: a current mirror circuit connecting a source of a fourth transistor to a second power supply voltage terminal.
(2)ゲートを信号入力端子と接続しドレインを第1の
電源電圧端子と接続した逆導電型の第5のトランジスタ
と、一端をこの第5のトランジスタのソースと接続し他
端を第2の電源電圧端子と接続した定電流源回路とを設
け、第1のトランジスタのゲートを前記第5のトランジ
スタのソースと接続した請求項(1)記載の増幅回路。
(2) a fifth transistor of opposite conductivity type whose gate is connected to the signal input terminal and whose drain is connected to the first power supply voltage terminal; one end is connected to the source of this fifth transistor and the other end is connected to the second transistor; 2. The amplifier circuit according to claim 1, further comprising a constant current source circuit connected to a power supply voltage terminal, and further comprising a gate of the first transistor connected to a source of the fifth transistor.
JP63042742A 1988-02-24 1988-02-24 Amplifier circuit Expired - Lifetime JPH0695614B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63042742A JPH0695614B2 (en) 1988-02-24 1988-02-24 Amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63042742A JPH0695614B2 (en) 1988-02-24 1988-02-24 Amplifier circuit

Publications (2)

Publication Number Publication Date
JPH01216607A true JPH01216607A (en) 1989-08-30
JPH0695614B2 JPH0695614B2 (en) 1994-11-24

Family

ID=12644471

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63042742A Expired - Lifetime JPH0695614B2 (en) 1988-02-24 1988-02-24 Amplifier circuit

Country Status (1)

Country Link
JP (1) JPH0695614B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007288646A (en) * 2006-04-19 2007-11-01 Sharp Corp Buffer circuit and solid-state imaging apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57166063A (en) * 1981-04-03 1982-10-13 Mitsubishi Electric Corp Semiconductor ic
JPS58111413A (en) * 1981-12-25 1983-07-02 Oki Electric Ind Co Ltd Cmos output circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57166063A (en) * 1981-04-03 1982-10-13 Mitsubishi Electric Corp Semiconductor ic
JPS58111413A (en) * 1981-12-25 1983-07-02 Oki Electric Ind Co Ltd Cmos output circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007288646A (en) * 2006-04-19 2007-11-01 Sharp Corp Buffer circuit and solid-state imaging apparatus

Also Published As

Publication number Publication date
JPH0695614B2 (en) 1994-11-24

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