JPS57157553A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57157553A
JPS57157553A JP56042961A JP4296181A JPS57157553A JP S57157553 A JPS57157553 A JP S57157553A JP 56042961 A JP56042961 A JP 56042961A JP 4296181 A JP4296181 A JP 4296181A JP S57157553 A JPS57157553 A JP S57157553A
Authority
JP
Japan
Prior art keywords
silver
terminal
layer
electrodes
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56042961A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6347149B2 (fa
Inventor
Keiichi Hirai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56042961A priority Critical patent/JPS57157553A/ja
Publication of JPS57157553A publication Critical patent/JPS57157553A/ja
Publication of JPS6347149B2 publication Critical patent/JPS6347149B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP56042961A 1981-03-24 1981-03-24 Semiconductor device Granted JPS57157553A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56042961A JPS57157553A (en) 1981-03-24 1981-03-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56042961A JPS57157553A (en) 1981-03-24 1981-03-24 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS57157553A true JPS57157553A (en) 1982-09-29
JPS6347149B2 JPS6347149B2 (fa) 1988-09-20

Family

ID=12650622

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56042961A Granted JPS57157553A (en) 1981-03-24 1981-03-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57157553A (fa)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5126644A (ja) * 1974-08-29 1976-03-05 Nippon Electric Co Metsukihoho

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5126644A (ja) * 1974-08-29 1976-03-05 Nippon Electric Co Metsukihoho

Also Published As

Publication number Publication date
JPS6347149B2 (fa) 1988-09-20

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