JPS5715555A - Digital telephone terminal - Google Patents

Digital telephone terminal

Info

Publication number
JPS5715555A
JPS5715555A JP8920280A JP8920280A JPS5715555A JP S5715555 A JPS5715555 A JP S5715555A JP 8920280 A JP8920280 A JP 8920280A JP 8920280 A JP8920280 A JP 8920280A JP S5715555 A JPS5715555 A JP S5715555A
Authority
JP
Japan
Prior art keywords
circuit
output
present
signal
inputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8920280A
Other languages
Japanese (ja)
Inventor
Tetsuo Takemura
Noboru Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8920280A priority Critical patent/JPS5715555A/en
Publication of JPS5715555A publication Critical patent/JPS5715555A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/253—Telephone sets using digital voice transmission

Abstract

PURPOSE:To reduce the number of bits of a buffer circuit and shift registers to half, by commonly using the buffer circuit which is provided independently for transmission and reception. CONSTITUTION:Buffer circuits 19, 20 are commonly used for transmission and reception through the use of selector circuits 21, 22. That is, the circuit 21 inputs the output of the circuit 19 to a code conversion circuit 2 when no selector control signal 23 is present, and the output of the circuit 20 to a code/decode circuit 7, and the output of the circuit 19 is inputted to the circuit 7 and the output of the circuit 20 to the circuit 2 when the signal 23 is present. The circuit 22 inputs the output of the circuit 7 to the circuit 20 and the output of the circuit 3 to the circuit 19 when no signal 23 is present, and the circuit 22 inputs the output of the circuit 7 to the circuit 19 and the output of the circuit 3 to the circuit 20, when the signal 23 is present.
JP8920280A 1980-07-02 1980-07-02 Digital telephone terminal Pending JPS5715555A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8920280A JPS5715555A (en) 1980-07-02 1980-07-02 Digital telephone terminal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8920280A JPS5715555A (en) 1980-07-02 1980-07-02 Digital telephone terminal

Publications (1)

Publication Number Publication Date
JPS5715555A true JPS5715555A (en) 1982-01-26

Family

ID=13964122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8920280A Pending JPS5715555A (en) 1980-07-02 1980-07-02 Digital telephone terminal

Country Status (1)

Country Link
JP (1) JPS5715555A (en)

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