JPS57152753A - Packet editing system - Google Patents

Packet editing system

Info

Publication number
JPS57152753A
JPS57152753A JP56037817A JP3781781A JPS57152753A JP S57152753 A JPS57152753 A JP S57152753A JP 56037817 A JP56037817 A JP 56037817A JP 3781781 A JP3781781 A JP 3781781A JP S57152753 A JPS57152753 A JP S57152753A
Authority
JP
Japan
Prior art keywords
packet
pkttr
signal
contents
lim
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56037817A
Other languages
Japanese (ja)
Inventor
Tokio Takai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP56037817A priority Critical patent/JPS57152753A/en
Publication of JPS57152753A publication Critical patent/JPS57152753A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems 
    • H04L12/56Packet switching systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To reduce the soft processing, by writing terminating side information to headers in respect to packets for which rewriting of contents of a call control memory LIM except call set and release is unnecessary when packets are inputted to a packet transaction (PKTTR). CONSTITUTION:When a packet comes, a start signal ST is inputted to a controller DMACTL to start the transfer of the packet to the PKTTR. A signal REO is issued from the controller DMACTL to transfer the packet in byte units. First, the first byte is set to a register RO, and it is discriminated whether rewriting of the header is necessary or not. If unnecessary, the signal REO and a count signal WCU of a write address counter WAC are issued to write the packet to the PKTTR as it is. If rewriting of the header is necessary, the third and the fourth bytes are set to registers R1 and R2 on a basis of the count value of a byte counter (BCNT) at set timings (S1 and S2) generated from a timer TIM, and contents of the LIM corresponding to these addresses are referred to. Thus, contents of the LIM are rewritten.
JP56037817A 1981-03-18 1981-03-18 Packet editing system Pending JPS57152753A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56037817A JPS57152753A (en) 1981-03-18 1981-03-18 Packet editing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56037817A JPS57152753A (en) 1981-03-18 1981-03-18 Packet editing system

Publications (1)

Publication Number Publication Date
JPS57152753A true JPS57152753A (en) 1982-09-21

Family

ID=12508071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56037817A Pending JPS57152753A (en) 1981-03-18 1981-03-18 Packet editing system

Country Status (1)

Country Link
JP (1) JPS57152753A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59198045A (en) * 1983-04-25 1984-11-09 Toyota Motor Corp Multiplex transmitter of signal
JPH0856239A (en) * 1994-08-12 1996-02-27 Nec Corp D-channel packet communication system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51138103A (en) * 1975-05-09 1976-11-29 Western Electric Co Packet exchanger

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51138103A (en) * 1975-05-09 1976-11-29 Western Electric Co Packet exchanger

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59198045A (en) * 1983-04-25 1984-11-09 Toyota Motor Corp Multiplex transmitter of signal
JPH0856239A (en) * 1994-08-12 1996-02-27 Nec Corp D-channel packet communication system

Similar Documents

Publication Publication Date Title
KR100337056B1 (en) Buffering data that flows between buses operating at different frequencies
CA2247341A1 (en) Asynchronous data pipe for automatically managing asynchronous data transfers between an application and a bus structure
GB1397692A (en) Machine memory systems
CA2192510A1 (en) Data Transmitting/Receiving Method Using Distributed Path Control in Data Switching System
EP0382358A3 (en) Full address and odd boundary direct memory access controller
JPS57152753A (en) Packet editing system
US4768210A (en) Method and apparatus for failsafe storage and reading of a digital counter in case of power interruption
JPS5690341A (en) Buffer switching system
JPS57135500A (en) Data memory protecting circuit
KR940006014A (en) Timer circuit with comparator
CS602090A3 (en) Method of packet communication in information system
JPS5720831A (en) Local burst transfer controlling system
JPS57162852A (en) Frame synchronizer
SU1591031A1 (en) Computer-subscriber interface
JPS5733472A (en) Memory access control system
JPS6134795A (en) Read only memory
SU1674140A2 (en) Input-output interface controller
SU1658165A1 (en) Device for interfacing information source to processor
JPS58218091A (en) Data transfer system
JPS58184647A (en) Data transfer system
KR950025552A (en) Interface method and apparatus in digital signal processing system
SU1524056A1 (en) Device for addressing a memory
JPS6118058A (en) Data transfer system
RU1807495C (en) Process-to-process interface
JPS6236933A (en) Frame phase correction circuit