JPS57152279A - Television receiver - Google Patents
Television receiverInfo
- Publication number
- JPS57152279A JPS57152279A JP56037509A JP3750981A JPS57152279A JP S57152279 A JPS57152279 A JP S57152279A JP 56037509 A JP56037509 A JP 56037509A JP 3750981 A JP3750981 A JP 3750981A JP S57152279 A JPS57152279 A JP S57152279A
- Authority
- JP
- Japan
- Prior art keywords
- memories
- signal
- horizontal period
- outputs
- supplied
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Systems (AREA)
Abstract
PURPOSE:To receive both TV signals of 2 systems whose number of horizontal scanning times is different and having simple configuration, by converting a TV signal of a standard system into a TV signal with the number of horizontal scanning times which is n times that of the standard TV signal. CONSTITUTION:A signal demodulated by a demodulator 2 is amplified after passing through LPF15 and supplied to analog memories 18, 20, 22, 24. The writing operation of the memories 18, 20 is set up the same horizontal period of a standard system. In reading operation, data are read from the memory 18 at a speed 2 times that of the writing operation during the first half of the next horizontal period and data are read from the memory 20 at the speed 2 times that of the writing operation during the last half of the same horizontal period. After one horizontal period from the operation of the memories 18, 20, the same operation is applied also to the memories 22, 24. The outputs of the memories 18, 20, 22, 24 are supplied to gate circuits 26-29 and the outputs of the gate circuits 26-29 are added by an adder 30. The outputs from the circuit 30 are amplified, converted into continuous analog signals and supplied to a relay switch 14.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56037509A JPS57152279A (en) | 1981-03-16 | 1981-03-16 | Television receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56037509A JPS57152279A (en) | 1981-03-16 | 1981-03-16 | Television receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57152279A true JPS57152279A (en) | 1982-09-20 |
Family
ID=12499494
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56037509A Pending JPS57152279A (en) | 1981-03-16 | 1981-03-16 | Television receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57152279A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63104585A (en) * | 1986-10-21 | 1988-05-10 | Sony Corp | Scan converter device for video signal |
-
1981
- 1981-03-16 JP JP56037509A patent/JPS57152279A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63104585A (en) * | 1986-10-21 | 1988-05-10 | Sony Corp | Scan converter device for video signal |
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