JPS57141123A - Bounding preventing circuit - Google Patents

Bounding preventing circuit

Info

Publication number
JPS57141123A
JPS57141123A JP56100827A JP10082781A JPS57141123A JP S57141123 A JPS57141123 A JP S57141123A JP 56100827 A JP56100827 A JP 56100827A JP 10082781 A JP10082781 A JP 10082781A JP S57141123 A JPS57141123 A JP S57141123A
Authority
JP
Japan
Prior art keywords
circuit
output
switch
bounding
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56100827A
Other languages
Japanese (ja)
Inventor
Yukio Kodama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56100827A priority Critical patent/JPS57141123A/en
Publication of JPS57141123A publication Critical patent/JPS57141123A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To prevent bounding by the AND output of the AND between a contact signal and the delay output of a counting circuit which starts counting when inputting the contact signal. CONSTITUTION:The output frequency of an oscillator 1 is divided by frequency dividers 21-29, and the resulting signal is supplied to a delay circuit 17. The circuit consists of an FF1- an FF4. The output of a switch 8 is applied to the reset terminal of the circuit 17 through an inverter 19. When the switch 8 is turned on, the output of the inverter 19 goes down to a low level and the circuit 17 starts counting. When the FF4 operates, an FF18 is set. When the FF18 is set, a gate 21 is opened and a high-level signal from the switch 8 is supplied to an electronic circuit through a gate 21.
JP56100827A 1981-06-29 1981-06-29 Bounding preventing circuit Pending JPS57141123A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56100827A JPS57141123A (en) 1981-06-29 1981-06-29 Bounding preventing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56100827A JPS57141123A (en) 1981-06-29 1981-06-29 Bounding preventing circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP49074693A Division JPS515079A (en) 1974-06-29 1974-06-29

Publications (1)

Publication Number Publication Date
JPS57141123A true JPS57141123A (en) 1982-09-01

Family

ID=14284150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56100827A Pending JPS57141123A (en) 1981-06-29 1981-06-29 Bounding preventing circuit

Country Status (1)

Country Link
JP (1) JPS57141123A (en)

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