JPS57132457A - Communication controlling system - Google Patents
Communication controlling systemInfo
- Publication number
- JPS57132457A JPS57132457A JP56017665A JP1766581A JPS57132457A JP S57132457 A JPS57132457 A JP S57132457A JP 56017665 A JP56017665 A JP 56017665A JP 1766581 A JP1766581 A JP 1766581A JP S57132457 A JPS57132457 A JP S57132457A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- reception
- transmission
- line
- control section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L13/00—Details of the apparatus or circuits covered by groups H04L15/00 or H04L17/00
- H04L13/02—Details not particular to receiver or transmitter
- H04L13/08—Intermediate storage means
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Communication Control (AREA)
Abstract
PURPOSE:To prevent confusion of communication between a station and an opposing station, by passing under-run or over-run state produced on a transmission and reception buffer on a data transmission/reception circuit, through the connection of a buffer controlling circuit to a timing forming circuit of a line individual control section. CONSTITUTION:A line common control section 1 is connected to a transmission line 3-1 and a reception line 3-2 via an individual line control section 2''. A data transmission/reception circuit 2-2 is connected to the control section 2'' via an interface circuit 2-3, and transmission and reception buffers 2-4 and 2-5 are connected to the circuit 2-2, and also a buffer controlling circuit 2-7 connected to a timing forming circuit 2-6 is connected to the circuit 2-2. Detection signals (a), (b) from the buffers 2-4, 2-5 are applied to the controlling circuit 2-7, transmission and reception buffer timings ST', RT' from the circuit 2-6 are applied to the control circuit 2-7 and the circuit 2-2, where under-run and over-run of transmission and reception are detected.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56017665A JPS57132457A (en) | 1981-02-09 | 1981-02-09 | Communication controlling system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56017665A JPS57132457A (en) | 1981-02-09 | 1981-02-09 | Communication controlling system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57132457A true JPS57132457A (en) | 1982-08-16 |
JPH038144B2 JPH038144B2 (en) | 1991-02-05 |
Family
ID=11950144
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56017665A Granted JPS57132457A (en) | 1981-02-09 | 1981-02-09 | Communication controlling system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57132457A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5846746A (en) * | 1981-09-12 | 1983-03-18 | Nec Corp | Circuit adaptor |
-
1981
- 1981-02-09 JP JP56017665A patent/JPS57132457A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5846746A (en) * | 1981-09-12 | 1983-03-18 | Nec Corp | Circuit adaptor |
Also Published As
Publication number | Publication date |
---|---|
JPH038144B2 (en) | 1991-02-05 |
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