JPS57124953A - Signal transmission device - Google Patents
Signal transmission deviceInfo
- Publication number
- JPS57124953A JPS57124953A JP1045681A JP1045681A JPS57124953A JP S57124953 A JPS57124953 A JP S57124953A JP 1045681 A JP1045681 A JP 1045681A JP 1045681 A JP1045681 A JP 1045681A JP S57124953 A JPS57124953 A JP S57124953A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- signal
- counter
- pulse
- reception
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
- Dc Digital Transmission (AREA)
Abstract
PURPOSE:To achieve a reception circuit which is not malfunctioned with noise, by converting a reception level signal into a pulse signal so that a reception output is produced when this pulse signal is counted for a prescribed number. CONSTITUTION:When a positive voltage is applied to a terminal 1 and a zero voltage level signal is given to a terminal 2, a sampling signal from a sampling pulse generator 5 is applied to gate circuit 3, 4, a counter 6 starts addition and applies a set signal to a set terminal of a flip-flop 10 when the prescribed number is counted. Thus, a reception output of logic ''1'' is obtained at an output terminal 11. In this case, if a terminal 2 changes to a positive potential level due to noise, a pulse is outputted from the gate 4 and applied to a counter 7 and a gate 8. The counter 7 is incremented by +1 and the counter 6 is set to the initial value. Thus, the counters 6, 7 repeat the addition of +1 and the initial set alternately by the pulse from the gates 3, 4, the flip-flop circuit 10 is subject to no change, and the output terminal 11 is kept at a positive level.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1045681A JPS57124953A (en) | 1981-01-27 | 1981-01-27 | Signal transmission device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1045681A JPS57124953A (en) | 1981-01-27 | 1981-01-27 | Signal transmission device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57124953A true JPS57124953A (en) | 1982-08-04 |
Family
ID=11750639
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1045681A Pending JPS57124953A (en) | 1981-01-27 | 1981-01-27 | Signal transmission device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57124953A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60124153U (en) * | 1984-01-31 | 1985-08-21 | パイオニア株式会社 | Data signal reading device |
-
1981
- 1981-01-27 JP JP1045681A patent/JPS57124953A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60124153U (en) * | 1984-01-31 | 1985-08-21 | パイオニア株式会社 | Data signal reading device |
JPH0326700Y2 (en) * | 1984-01-31 | 1991-06-10 |
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