JPS57121319A - Analogue-digital converter - Google Patents

Analogue-digital converter

Info

Publication number
JPS57121319A
JPS57121319A JP592681A JP592681A JPS57121319A JP S57121319 A JPS57121319 A JP S57121319A JP 592681 A JP592681 A JP 592681A JP 592681 A JP592681 A JP 592681A JP S57121319 A JPS57121319 A JP S57121319A
Authority
JP
Japan
Prior art keywords
frq
conversion
multiplexer
converted
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP592681A
Other languages
Japanese (ja)
Inventor
Tetsuo Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Fuji Facom Corp
Original Assignee
Fuji Electric Co Ltd
Fuji Facom Corp
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Facom Corp, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP592681A priority Critical patent/JPS57121319A/en
Publication of JPS57121319A publication Critical patent/JPS57121319A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To insulate the input and the output from each other completely and secure the simultaneity of conversion data, by counting plural input signals through an insulating circuit by a multichannel pulse counting device after subjecting them to voltage-frequency conversion.
CONSTITUTION: Analogue input signals a1∼an are converted to frequencies FRQ1∼FRQn by voltage-frequency converters 2'-1∼2'-n and are applied to a multiplexer 1' through insulating circuits 6-1∼6-n. When a command signal STT for the start of A/D conversion is given from a central processor CPU to an A/D conversion controlling circuit 3, the controlling circuit 3 takes out selectively contents of the multiplexer 1' and an n×N-bit memory 7, and pulse train signals FRQ1∼FRQn are counted for a constant time and are converted to digital values.
COPYRIGHT: (C)1982,JPO&Japio
JP592681A 1981-01-20 1981-01-20 Analogue-digital converter Pending JPS57121319A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP592681A JPS57121319A (en) 1981-01-20 1981-01-20 Analogue-digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP592681A JPS57121319A (en) 1981-01-20 1981-01-20 Analogue-digital converter

Publications (1)

Publication Number Publication Date
JPS57121319A true JPS57121319A (en) 1982-07-28

Family

ID=11624489

Family Applications (1)

Application Number Title Priority Date Filing Date
JP592681A Pending JPS57121319A (en) 1981-01-20 1981-01-20 Analogue-digital converter

Country Status (1)

Country Link
JP (1) JPS57121319A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02216915A (en) * 1989-02-16 1990-08-29 Yokogawa Electric Corp Multi-point measuring instrument
US8342702B2 (en) 2007-10-16 2013-01-01 Honda Motor Co., Ltd. Vehicle door mirror mount structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02216915A (en) * 1989-02-16 1990-08-29 Yokogawa Electric Corp Multi-point measuring instrument
US8342702B2 (en) 2007-10-16 2013-01-01 Honda Motor Co., Ltd. Vehicle door mirror mount structure

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