JPS57121249A - Method of suppressing parasitic side wall transistor in locos structure - Google Patents
Method of suppressing parasitic side wall transistor in locos structureInfo
- Publication number
- JPS57121249A JPS57121249A JP56194603A JP19460381A JPS57121249A JP S57121249 A JPS57121249 A JP S57121249A JP 56194603 A JP56194603 A JP 56194603A JP 19460381 A JP19460381 A JP 19460381A JP S57121249 A JPS57121249 A JP S57121249A
- Authority
- JP
- Japan
- Prior art keywords
- side wall
- locos structure
- suppressing parasitic
- parasitic side
- wall transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/219,015 US4373965A (en) | 1980-12-22 | 1980-12-22 | Suppression of parasitic sidewall transistors in locos structures |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57121249A true JPS57121249A (en) | 1982-07-28 |
JPH0346976B2 JPH0346976B2 (ja) | 1991-07-17 |
Family
ID=22817457
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56194603A Granted JPS57121249A (en) | 1980-12-22 | 1981-12-04 | Method of suppressing parasitic side wall transistor in locos structure |
Country Status (2)
Country | Link |
---|---|
US (1) | US4373965A (ja) |
JP (1) | JPS57121249A (ja) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4472874A (en) * | 1981-06-10 | 1984-09-25 | Tokyo Shibaura Denki Kabushiki Kaisha | Method of forming planar isolation regions having field inversion regions |
US4511911A (en) * | 1981-07-22 | 1985-04-16 | International Business Machines Corporation | Dense dynamic memory cell structure and process |
US4563227A (en) * | 1981-12-08 | 1986-01-07 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing a semiconductor device |
US4569698A (en) * | 1982-02-25 | 1986-02-11 | Raytheon Company | Method of forming isolated device regions by selective successive etching of composite masking layers and semiconductor material prior to ion implantation |
DE3329074A1 (de) * | 1983-08-11 | 1985-02-28 | Siemens AG, 1000 Berlin und 8000 München | Verhinderung der oxidationsmitteldiffusion bei der herstellung von halbleiterschichtanordnungen |
US4477310A (en) * | 1983-08-12 | 1984-10-16 | Tektronix, Inc. | Process for manufacturing MOS integrated circuit with improved method of forming refractory metal silicide areas |
US4547793A (en) * | 1983-12-27 | 1985-10-15 | International Business Machines Corporation | Trench-defined semiconductor structure |
US4516316A (en) * | 1984-03-27 | 1985-05-14 | Advanced Micro Devices, Inc. | Method of making improved twin wells for CMOS devices by controlling spatial separation |
US4574469A (en) * | 1984-09-14 | 1986-03-11 | Motorola, Inc. | Process for self-aligned buried layer, channel-stop, and isolation |
US4583282A (en) * | 1984-09-14 | 1986-04-22 | Motorola, Inc. | Process for self-aligned buried layer, field guard, and isolation |
US4702000A (en) * | 1986-03-19 | 1987-10-27 | Harris Corporation | Technique for elimination of polysilicon stringers in direct moat field oxide structure |
US4818725A (en) * | 1986-09-15 | 1989-04-04 | Harris Corp. | Technique for forming planarized gate structure |
US4855258A (en) * | 1987-10-22 | 1989-08-08 | Ncr Corporation | Native oxide reduction for sealing nitride deposition |
US4814290A (en) * | 1987-10-30 | 1989-03-21 | International Business Machines Corporation | Method for providing increased dopant concentration in selected regions of semiconductor devices |
US4812418A (en) * | 1987-11-27 | 1989-03-14 | Motorola, Inc. | Micron and submicron patterning without using a lithographic mask having submicron dimensions |
KR910010043B1 (ko) * | 1988-07-28 | 1991-12-10 | 한국전기통신공사 | 스페이서를 이용한 미세선폭 형성방법 |
US5348910A (en) * | 1991-12-24 | 1994-09-20 | Seiko Epson Corporation | Method of manufacturing a semiconductor device and the product thereby |
US5328866A (en) * | 1992-09-21 | 1994-07-12 | Siliconix Incorporated | Low temperature oxide layer over field implant mask |
US5439842A (en) * | 1992-09-21 | 1995-08-08 | Siliconix Incorporated | Low temperature oxide layer over field implant mask |
JPH06349820A (ja) * | 1993-06-11 | 1994-12-22 | Rohm Co Ltd | 半導体装置の製造方法 |
KR0138234B1 (ko) * | 1994-02-24 | 1998-04-28 | 김광호 | 고전압 모오스 트랜지스터의 구조 |
US6627511B1 (en) | 1995-07-28 | 2003-09-30 | Motorola, Inc. | Reduced stress isolation for SOI devices and a method for fabricating |
US8603870B2 (en) | 1996-07-11 | 2013-12-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
TW556263B (en) * | 1996-07-11 | 2003-10-01 | Semiconductor Energy Lab | Semiconductor device and method of manufacturing the same |
US7981759B2 (en) * | 2007-07-11 | 2011-07-19 | Paratek Microwave, Inc. | Local oxidation of silicon planarization for polysilicon layers under thin film structures |
TWI588918B (zh) * | 2014-04-01 | 2017-06-21 | 亞太優勢微系統股份有限公司 | 具精確間隙機電晶圓結構與及其製作方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5535888U (ja) * | 1978-08-30 | 1980-03-07 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL170901C (nl) * | 1971-04-03 | 1983-01-03 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting. |
JPS5228550B2 (ja) * | 1972-10-04 | 1977-07-27 | ||
GB1457139A (en) * | 1973-09-27 | 1976-12-01 | Hitachi Ltd | Method of manufacturing semiconductor device |
US4137109A (en) * | 1976-04-12 | 1979-01-30 | Texas Instruments Incorporated | Selective diffusion and etching method for isolation of integrated logic circuit |
NL185376C (nl) * | 1976-10-25 | 1990-03-16 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting. |
US4135289A (en) * | 1977-08-23 | 1979-01-23 | Bell Telephone Laboratories, Incorporated | Method for producing a buried junction memory device |
US4182636A (en) * | 1978-06-30 | 1980-01-08 | International Business Machines Corporation | Method of fabricating self-aligned contact vias |
-
1980
- 1980-12-22 US US06/219,015 patent/US4373965A/en not_active Expired - Fee Related
-
1981
- 1981-12-04 JP JP56194603A patent/JPS57121249A/ja active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5535888U (ja) * | 1978-08-30 | 1980-03-07 |
Also Published As
Publication number | Publication date |
---|---|
US4373965A (en) | 1983-02-15 |
JPH0346976B2 (ja) | 1991-07-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS57121249A (en) | Method of suppressing parasitic side wall transistor in locos structure | |
JPS56130918A (en) | Method of injecting semiconductor | |
GB2077493B (en) | Mos transistor | |
JPS56110261A (en) | Method of manufacturing bipolar transistor | |
JPS56164580A (en) | Method of producing transistor device | |
PL239558A1 (en) | Method of manufacture of alkylene carbonates | |
DE3175383D1 (en) | Integrated power transistor | |
DE3165937D1 (en) | Method of making an integrated planar transistor | |
JPS57123026A (en) | Method of laminating aramide-water leave | |
JPS57133682A (en) | Method of producing field effect transistor | |
JPS56122163A (en) | Method of manufacturing selffaligned lateral bipolar transistor | |
JPS56146274A (en) | Method of manufacturing bipolar transistor | |
GB2074374B (en) | Method of making field effect transistors | |
CS221985B2 (en) | Fungicide means and method of making the active substan ce | |
JPS56145237A (en) | Isolation of monochloroacetaldehyde | |
JPS5752170A (en) | Power transistor | |
EP0180363A3 (en) | Horizontal structure transistor and method of fabrication | |
JPS56135642A (en) | Connecting method of precast box carvert | |
JPS5625557A (en) | Method of temporarily fitting drain | |
JPS5748061A (en) | Application of simple vibrationproof floating floor | |
GB2089565B (en) | Transistors | |
SU1018461A1 (ru) | Способ возведения стены в грунте | |
GB8322843D0 (en) | Method of construction | |
DE3162251D1 (en) | Method of making drain trenches | |
JPS56167055A (en) | Erection of hand rail |