JPS57115052A - Multiplex concentrator and alloter device - Google Patents

Multiplex concentrator and alloter device

Info

Publication number
JPS57115052A
JPS57115052A JP124281A JP124281A JPS57115052A JP S57115052 A JPS57115052 A JP S57115052A JP 124281 A JP124281 A JP 124281A JP 124281 A JP124281 A JP 124281A JP S57115052 A JPS57115052 A JP S57115052A
Authority
JP
Japan
Prior art keywords
alloter
signal
modem interface
concentrator
multiplex
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP124281A
Other languages
Japanese (ja)
Inventor
Kenzo Osami
Fumio Akiyama
Fusayoshi Aso
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP124281A priority Critical patent/JPS57115052A/en
Publication of JPS57115052A publication Critical patent/JPS57115052A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/50—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication
    • H04L12/52—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication using time division techniques
    • H04L12/525—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication using time division techniques involving a stored program control

Abstract

PURPOSE:To prevent the occurrence of the error due to a bit failure, by encoding and transmitting a MODEM interface signal in a multiplex concentrator and alloter device. CONSTITUTION:A control part 20 of a multiplex concentrator and alloter device 10 encodes the MODEM interface signal to an 8-bit code signal by an encoding/ decoding circuit 23 and transmits this code signal through a trunk circuit corresponding part 22 to a multiplex concentrator and alloter device 3 directed by a control information channel on a trunk circuit. In this transmission, since the signal is encode and is difficult to receive the influence of a bit failure, control information is transmitted only once. Meanwhile, this control information is received by the control part 20 of the multiplex concentrator and alloter device 3 and is restored to the original MODEM interface signal by the encoding/decoding circuit 23. The control part 20 checks the parity of the received code; and if an error is detected, the control part 20 suspends the control operation due to the transmitted MODEM interface signal.
JP124281A 1981-01-09 1981-01-09 Multiplex concentrator and alloter device Pending JPS57115052A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP124281A JPS57115052A (en) 1981-01-09 1981-01-09 Multiplex concentrator and alloter device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP124281A JPS57115052A (en) 1981-01-09 1981-01-09 Multiplex concentrator and alloter device

Publications (1)

Publication Number Publication Date
JPS57115052A true JPS57115052A (en) 1982-07-17

Family

ID=11495984

Family Applications (1)

Application Number Title Priority Date Filing Date
JP124281A Pending JPS57115052A (en) 1981-01-09 1981-01-09 Multiplex concentrator and alloter device

Country Status (1)

Country Link
JP (1) JPS57115052A (en)

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