JPS57109194A - Rom test circuit - Google Patents

Rom test circuit

Info

Publication number
JPS57109194A
JPS57109194A JP18470780A JP18470780A JPS57109194A JP S57109194 A JPS57109194 A JP S57109194A JP 18470780 A JP18470780 A JP 18470780A JP 18470780 A JP18470780 A JP 18470780A JP S57109194 A JPS57109194 A JP S57109194A
Authority
JP
Japan
Prior art keywords
address
test
rom5
data
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18470780A
Other languages
Japanese (ja)
Inventor
Masayuki Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18470780A priority Critical patent/JPS57109194A/en
Publication of JPS57109194A publication Critical patent/JPS57109194A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals

Landscapes

  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To enable the test of ROM data check circuit, by storing error state data to an existing ROM at all times. CONSTITUTION:When a selector switch 1 is selected to the test side, ''1'' is inputted from a control power supply VC2 to a test mode register 2, and ''0'' is inputted from a control power supply VC1 at operation. ''0'' of the most significant address A0 in the address of an ROM5 is given to an ROM5 from the register 2 according to the clock signal CLK. The switch 1 gives start signal to a control circuit 3 at test, address signals A1-An are given to an address register 4, the error data stored in the error data area ERD of the ROM5 is read out at a check circuit 6 for checking. The A0 of the normal data is stored in the data area DAT of ''0''.
JP18470780A 1980-12-25 1980-12-25 Rom test circuit Pending JPS57109194A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18470780A JPS57109194A (en) 1980-12-25 1980-12-25 Rom test circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18470780A JPS57109194A (en) 1980-12-25 1980-12-25 Rom test circuit

Publications (1)

Publication Number Publication Date
JPS57109194A true JPS57109194A (en) 1982-07-07

Family

ID=16157956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18470780A Pending JPS57109194A (en) 1980-12-25 1980-12-25 Rom test circuit

Country Status (1)

Country Link
JP (1) JPS57109194A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6070600A (en) * 1983-09-28 1985-04-22 Nippon Signal Co Ltd:The Microcomputer system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6070600A (en) * 1983-09-28 1985-04-22 Nippon Signal Co Ltd:The Microcomputer system

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