JPS57109115A - Peak shift display device - Google Patents

Peak shift display device

Info

Publication number
JPS57109115A
JPS57109115A JP18649880A JP18649880A JPS57109115A JP S57109115 A JPS57109115 A JP S57109115A JP 18649880 A JP18649880 A JP 18649880A JP 18649880 A JP18649880 A JP 18649880A JP S57109115 A JPS57109115 A JP S57109115A
Authority
JP
Japan
Prior art keywords
peak shift
data
edge
latched
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18649880A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0221042B2 (enExample
Inventor
Masato Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP18649880A priority Critical patent/JPS57109115A/ja
Publication of JPS57109115A publication Critical patent/JPS57109115A/ja
Publication of JPH0221042B2 publication Critical patent/JPH0221042B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
    • G11B20/10212—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter compensation for data shift, e.g. pulse-crowding effects

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Digital Magnetic Recording (AREA)
  • Dc Digital Transmission (AREA)
JP18649880A 1980-12-26 1980-12-26 Peak shift display device Granted JPS57109115A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18649880A JPS57109115A (en) 1980-12-26 1980-12-26 Peak shift display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18649880A JPS57109115A (en) 1980-12-26 1980-12-26 Peak shift display device

Publications (2)

Publication Number Publication Date
JPS57109115A true JPS57109115A (en) 1982-07-07
JPH0221042B2 JPH0221042B2 (enExample) 1990-05-11

Family

ID=16189534

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18649880A Granted JPS57109115A (en) 1980-12-26 1980-12-26 Peak shift display device

Country Status (1)

Country Link
JP (1) JPS57109115A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2505705A (en) * 2012-09-10 2014-03-12 St Microelectronics Res & Dev Circuit for combining signals comprising a plurality of edge detectors

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5132962A (enExample) * 1974-06-20 1976-03-19 Westinghouse Electric Corp

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5132962A (enExample) * 1974-06-20 1976-03-19 Westinghouse Electric Corp

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2505705A (en) * 2012-09-10 2014-03-12 St Microelectronics Res & Dev Circuit for combining signals comprising a plurality of edge detectors
US9007118B2 (en) 2012-09-10 2015-04-14 STMicroelctronics (Research & Development) Limited Circuit for combining signals

Also Published As

Publication number Publication date
JPH0221042B2 (enExample) 1990-05-11

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