JPS5710875A - Instruction control device - Google Patents
Instruction control deviceInfo
- Publication number
- JPS5710875A JPS5710875A JP8611380A JP8611380A JPS5710875A JP S5710875 A JPS5710875 A JP S5710875A JP 8611380 A JP8611380 A JP 8611380A JP 8611380 A JP8611380 A JP 8611380A JP S5710875 A JPS5710875 A JP S5710875A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- register
- operation processing
- control device
- overlapped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
- G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
Abstract
PURPOSE:To increase a processing speed of an operation processing means of a pipeline structure, by constituting a device so that instructing information to the same instruction can be overlapped and held by the respective instruction holding means for dividing an operation control execution stage into plural parts. CONSTITUTION:An operation control execution stage in an instruction control device is divided into two, an instruction is set to an EW stage register 10 by a timing signal of a counter 12 having a timing counting circuit, and by a timing signal of counters 15, 18 having an element counting circuit, instructions which have been set already to an ER register 8 and an EW register 10, respectively, are erased, and the next instruction is set. For instance, between time t1'-t2' and between t3'-t4', the instructing information is overlapped to the registers 8, 10 so that it can be held. In this way, in case of a lot of elements to be processed, the operation processing speed is increased by removing an idle state of the operation processing part of a pipeline structure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8611380A JPS5710875A (en) | 1980-06-25 | 1980-06-25 | Instruction control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8611380A JPS5710875A (en) | 1980-06-25 | 1980-06-25 | Instruction control device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5710875A true JPS5710875A (en) | 1982-01-20 |
JPS6116114B2 JPS6116114B2 (en) | 1986-04-28 |
Family
ID=13877636
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8611380A Granted JPS5710875A (en) | 1980-06-25 | 1980-06-25 | Instruction control device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5710875A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS592143A (en) * | 1982-06-29 | 1984-01-07 | Hitachi Ltd | Operation controlling system |
-
1980
- 1980-06-25 JP JP8611380A patent/JPS5710875A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS592143A (en) * | 1982-06-29 | 1984-01-07 | Hitachi Ltd | Operation controlling system |
JPH0157817B2 (en) * | 1982-06-29 | 1989-12-07 | Hitachi Ltd |
Also Published As
Publication number | Publication date |
---|---|
JPS6116114B2 (en) | 1986-04-28 |
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