JPS5710852A - Main memory control system - Google Patents

Main memory control system

Info

Publication number
JPS5710852A
JPS5710852A JP8346080A JP8346080A JPS5710852A JP S5710852 A JPS5710852 A JP S5710852A JP 8346080 A JP8346080 A JP 8346080A JP 8346080 A JP8346080 A JP 8346080A JP S5710852 A JPS5710852 A JP S5710852A
Authority
JP
Japan
Prior art keywords
address
unit
main memory
information
display information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8346080A
Other languages
Japanese (ja)
Inventor
Teruo Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8346080A priority Critical patent/JPS5710852A/en
Publication of JPS5710852A publication Critical patent/JPS5710852A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)

Abstract

PURPOSE:To initialize so that the whole main memory area becomes a load object, by detaching a memory unit which has been connected before the initializing operation, and has a partial fault, and giving continuous addresses to that which has no fault and is being connected. CONSTITUTION:On a system is provided a memory device 5 consisting of plural memory units having a unit number. For the purpose of access of the device 5, in an address converter 35 are stored plural converting information for converting the address information consisting of an address number part which is given by an address buffer 31 of a main memory device 3, and an address part in a unit, to address information consisting of a unit number part and an address part in a unit, and also plural pairs of effectiveness display information and partial fault display information of a unit. In response to a relief type initializing command, the address number part is made continuous addresses to a unit displaying that display information in the address converter 35 is effective and also free from partial fault.
JP8346080A 1980-06-21 1980-06-21 Main memory control system Pending JPS5710852A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8346080A JPS5710852A (en) 1980-06-21 1980-06-21 Main memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8346080A JPS5710852A (en) 1980-06-21 1980-06-21 Main memory control system

Publications (1)

Publication Number Publication Date
JPS5710852A true JPS5710852A (en) 1982-01-20

Family

ID=13803068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8346080A Pending JPS5710852A (en) 1980-06-21 1980-06-21 Main memory control system

Country Status (1)

Country Link
JP (1) JPS5710852A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62280945A (en) * 1986-05-30 1987-12-05 Fujitsu Ltd Memory system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62280945A (en) * 1986-05-30 1987-12-05 Fujitsu Ltd Memory system

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